tx_fifo.lpc

来自「在通讯领域中使用相当广泛的HDLC」· LPC 代码 · 共 41 行

[Device]
Family=ep5g00
PartType=LFEC20E
PartName=LFEC20E-4F484CES
SpeedGrade=-4
Package=FPBGA484
OperatingCondition=COM
Status=P

[IP]
VendorName=Lattice Semiconductor Corporation
CoreType=LPM
CoreStatus=Demo
CoreName=FIFO_DC
CoreRevision=1.0
ModuleName=TX_FIFO
SourceFormat=Schematic/VHDL
ParameterFileVersion=1.0
Date=04/28/2005
Time=17:44:19

[Parameters]
Verilog=0
VHDL=1
EDIF=1
Destination=Synplicity
Expression=BusA[0 to 7]
Order=Big Endian [MSB:LSB]
IO=0
Depth=512
Width=8
pe=4
pf=250
inPipeline=0
outPipeline=0
MOR=0
InData=Registered
Expression=BusA[0 to 7]
EDIF=1
regout=0