rx_cnt_fifo.vhd

在通讯领域中使用相当广泛的HDLC

        A                    =>  rCntNBQ5);

    regInst1: FD1S3DX
        PORT MAP (
        Q                    =>  eEqReg10,
        CD                   =>  Reset,
        CK                   =>  RdClock,
        D                    =>  eEqReg00);

    regInst27: FD1S3DX
        PORT MAP (
        Q                    =>  fEqReg04,
        CD                   =>  Reset,
        CK                   =>  WrClock,
        D                    =>  RdAddress4);

    regInst32: FD1S3DX
        PORT MAP (
        Q                    =>  fEqReg16,
        CD                   =>  Reset,
        CK                   =>  WrClock,
        D                    =>  fEqReg06);

    WrAddrGen_xorGB1_I000000: VHI
        PORT MAP (
        Z                    =>  WrAddrGen_xorGB1_VCC);

    WrAddrGen_xorBG5_I000000: VHI
        PORT MAP (
        Z                    =>  WrAddrGen_xorBG5_VCC);

    aeSubXor2_I000000: VHI
        PORT MAP (
        Z                    =>  aeSubXor2_VCC);

    regInst28: FD1S3DX
        PORT MAP (
        Q                    =>  fEqReg14,
        CD                   =>  Reset,
        CK                   =>  WrClock,
        D                    =>  fEqReg04);

    aeSubXor_inst1: ORCALUT4
        GENERIC MAP (
        INIT => X"6000")
        PORT MAP (
        Z                    =>  aeSub8,
        D                    =>  aeSubXor_VCC,
        C                    =>  aeSubXor_VCC,
        B                    =>  rad8,
        A                    =>  eEqReg18);

    aeLEInst_agbInst4: ALEB2
        PORT MAP (
        LE                   =>  aeLEOut,
        CI                   =>  aeLEInst_agbOut3,
        B1                   =>  aeLEInst_GND,
        B0                   =>  GND,
        A1                   =>  aeLEInst_GND,
        A0                   =>  aeSubOut8);

    WrAddrGen_ffInst1: FD1S3DX
        PORT MAP (
        Q                    =>  WrAddress1,
        CD                   =>  Reset,
        CK                   =>  WrClock,
        D                    =>  wCntGBQ1);

    WrAddrGen_bufInst0: BUFBA
        PORT MAP (
        Z                    =>  WrAddrGen_BINQ8,
        A                    =>  wCntQ8);

    WrAddrGen_xorGB2_I000000: VHI
        PORT MAP (
        Z                    =>  WrAddrGen_xorGB2_VCC);

    WrAddrGen_xorBG6_I000000: VHI
        PORT MAP (
        Z                    =>  WrAddrGen_xorBG6_VCC);

    aeSubXor3_I000000: VHI
        PORT MAP (
        Z                    =>  aeSubXor3_VCC);

    fullEQ_xnor4BitEQ0_inst0: ORCALUT4
        GENERIC MAP (
        INIT => X"9009")
        PORT MAP (
        Z                    =>  fullEQ_xnor4BitEQ0_Int0,
        D                    =>  fEqReg11,
        C                    =>  wCntGBQ1,
        B                    =>  fEqReg10,
        A                    =>  wCntGBQ0);

    RdAddrGen_cAdder_vgbAdderInst2_Adder: FADD2
        PORT MAP (
        S1                   =>  RdAddrGen_cAdder_vgbAdderInst2_tmp0,
        S0                   =>  RdAddrGen_NBQ8,
        COUT1                =>  RdAddrGen_cAdder_vgbAdderInst2_tmp1,
        CI                   =>  RdAddrGen_cAdder_Cout8,
        B1                   =>  RdAddrGen_cAdder_vgbAdderInst2_GND,
        B0                   =>  RdAddrGen_GND,
        A1                   =>  RdAddrGen_cAdder_vgbAdderInst2_GND,
        A0                   =>  RdAddrGen_BINQ8);

    RdAddrGen_xorGB1_I000000: VHI
        PORT MAP (
        Z                    =>  RdAddrGen_xorGB1_VCC);

    RdAddrGen_xorBG5_I000000: VHI
        PORT MAP (
        Z                    =>  RdAddrGen_xorBG5_VCC);

    ffwMsbInst: FD1S3DX
        PORT MAP (
        Q                    =>  WrAddress7,
        CD                   =>  Reset,
        CK                   =>  WrClock,
        D                    =>  wadmsb);

    regInst3: FD1S3DX
        PORT MAP (
        Q                    =>  eEqReg11,
        CD                   =>  Reset,
        CK                   =>  RdClock,
        D                    =>  eEqReg01);

    regInst29: FD1S3DX
        PORT MAP (
        Q                    =>  fEqReg05,
        CD                   =>  Reset,
        CK                   =>  WrClock,
        D                    =>  RdAddress5);

    regInst34: FD1S3DX
        PORT MAP (
        Q                    =>  fEqReg17,
        CD                   =>  Reset,
        CK                   =>  WrClock,
        D                    =>  fEqReg07);

    WrAddrGen_bufInst1: BUFBA
        PORT MAP (
        Z                    =>  wad8,
        A                    =>  WrAddrGen_NBQ8);

    WrAddrGen_xorGB3_I000000: VHI
        PORT MAP (
        Z                    =>  WrAddrGen_xorGB3_VCC);

    WrAddrGen_xorBG7_I000000: VHI
        PORT MAP (
        Z                    =>  WrAddrGen_xorBG7_VCC);

    aeSubXor4_I000000: VHI
        PORT MAP (
        Z                    =>  aeSubXor4_VCC);

    aeSub_vgbAdderInst2_I000000: VLO
        PORT MAP (
        Z                    =>  aeSub_vgbAdderInst2_GND);

    emptyEQ_xnor4BitEQ1_inst0: ORCALUT4
        GENERIC MAP (
        INIT => X"9009")
        PORT MAP (
        Z                    =>  emptyEQ_xnor4BitEQ1_Int0,
        D                    =>  eEqReg15,
        C                    =>  rCntGBQ5,
        B                    =>  eEqReg14,
        A                    =>  rCntGBQ4);

    xorwmsb_I000000: VHI
        PORT MAP (
        Z                    =>  xorwmsb_VCC);

    RdAddrGen_xorGB3_I000000: VHI
        PORT MAP (
        Z                    =>  RdAddrGen_xorGB3_VCC);

    RdAddrGen_xorBG7_I000000: VHI
        PORT MAP (
        Z                    =>  RdAddrGen_xorBG7_VCC);

    RdAddrGen_xorGB5_inst1: ORCALUT4
        GENERIC MAP (
        INIT => X"6000")
        PORT MAP (
        Z                    =>  RdAddrGen_BINQ5,
        D                    =>  RdAddrGen_xorGB5_VCC,
        C                    =>  RdAddrGen_xorGB5_VCC,
        B                    =>  RdAddrGen_BINQ6,
        A                    =>  RdAddress5);

    xorEEQ_inst1: ORCALUT4
        GENERIC MAP (
        INIT => X"6000")
        PORT MAP (
        Z                    =>  eEqmsb,
        D                    =>  xorEEQ_VCC,
        C                    =>  xorEEQ_VCC,
        B                    =>  eEqReg18,
        A                    =>  eEqReg17);

    emptyEQ_xnor4BitEQ1_inst1: ORCALUT4
        GENERIC MAP (
        INIT => X"9009")
        PORT MAP (
        Z                    =>  emptyEQ_xnor4BitEQ1_Int1,
        D                    =>  eEqmsb,
        C                    =>  radmsb,
        B                    =>  eEqReg16,
        A                    =>  rCntGBQ6);

    WrAddrGen_xorGB5_I000000: VHI
        PORT MAP (
        Z                    =>  WrAddrGen_xorGB5_VCC);

    afSub_vgbAdderInst2_Sub0: FSUB2
        PORT MAP (
        S1                   =>  afSub_vgbAdderInst2_tmp1,
        S0                   =>  afSubOut8,
        BOUT1                =>  afSub_vgbAdderInst2_tmp0,
        BOUT0                =>  afSub_Cout,
        BI                   =>  afSub_Cout8,
        B1                   =>  afSub_vgbAdderInst2_GND,
        B0                   =>  GND,
        A1                   =>  afSub_vgbAdderInst2_GND,
        A0                   =>  afSub8);

    RdAddrGen_I000000: VLO
        PORT MAP (
        Z                    =>  RdAddrGen_GND);

    RdAddrGen_xorBG2_inst1: ORCALUT4
        GENERIC MAP (
        INIT => X"6000")
        PORT MAP (
        Z                    =>  rCntGBQ2,
        D                    =>  RdAddrGen_xorBG2_VCC,
        C                    =>  RdAddrGen_xorBG2_VCC,
        B                    =>  rCntNBQ3,
        A                    =>  rCntNBQ2);

    aeSubXor6_I000000: VHI
        PORT MAP (
        Z                    =>  aeSubXor6_VCC);

    RdAddrGen_xorGB5_I000000: VHI
        PORT MAP (
        Z                    =>  RdAddrGen_xorGB5_VCC);

    xorEEQ_I000000: VHI
        PORT MAP (
        Z                    =>  xorEEQ_VCC);

    emptyEQ_xnor4BitEQ1_I000000: VLO
        PORT MAP (
        Z                    =>  emptyEQ_xnor4BitEQ1_GND);

    RdAddrGen_xorGB6_I000000: VHI
        PORT MAP (
        Z                    =>  RdAddrGen_xorGB6_VCC);

    regInst8: FD1S3DX
        PORT MAP (
        Q                    =>  eEqReg04,
        CD                   =>  Reset,
        CK                   =>  RdClock,
        D                    =>  WrAddress4);

    regInst39: FD1S3BX
        PORT MAP (
        Q                    =>  AlmostEmpty,
        PD                   =>  Reset,
        CK                   =>  RdClock,
        D                    =>  aeLEOut);

    WrAddrGen_xorGB7_I000000: VHI
        PORT MAP (
        Z                    =>  WrAddrGen_xorGB7_VCC);

    WrAddrGen_ffInst6: FD1S3DX
        PORT MAP (
        Q                    =>  WrAddress6,
        CD                   =>  Reset,
        CK                   =>  WrClock,
        D                    =>  wCntGBQ6);

    afSubXor5_inst1: ORCALUT4
        GENERIC MAP (
        INIT => X"6000")
        PORT MAP (
        Z                    =>  afSub5,
        D                    =>  afSubXor5_VCC,
        C                    =>  afSubXor5_VCC,
        B                    =>  afSub6,
        A                    =>  fEqReg15);

    RdAddrGen_cAdder_vgbAdderInst2_I000000: VLO
        PORT MAP (
        Z                    =>  RdAddrGen_cAdder_vgbAdderInst2_GND);

    RdAddrGen_ffInst1: FD1S3DX
        PORT MAP (
        Q                    =>  RdAddress1,
        CD                   =>  Reset,
        CK                   =>  RdClock,
        D                    =>  rCntGBQ1);

    aeSub_vgbAdderInst1_Sub0: FSUB2
        PORT MAP (
        S1                   =>  aeSubOut5,
        S0                   =>  aeSubOut4,
        BOUT1                =>  aeSub_vgbAdderInst1_Cout0,
        BOUT0                =>  aeSub_vgbAdderInst1_tmp0,
        BI                   =>  aeSub_Cout4,
        B1                   =>  rCntNBQ5,
        B0                   =>  rCntNBQ4,
        A1                   =>  aeSub5,
        A0                   =>  aeSub4);

    afSub_vgbAdderInst2_I000000: VLO
        PORT MAP (
        Z                    =>  afSub_vgbAdderInst2_GND);

    I000000: VHI
        PORT MAP (
        Z                    =>  VCC);