📄 rx_cnt_fifo.vhd
字号:
C => eandbInst_VCC,
B => RdEn,
A => Empty_sig);
regInst15: FD1S3DX
PORT MAP (
Q => eEqReg17,
CD => Reset,
CK => RdClock,
D => eEqReg07);
regInst20: FD1S3DX
PORT MAP (
Q => fEqReg10,
CD => Reset,
CK => WrClock,
D => fEqReg00);
xorrmsb_inst1: ORCALUT4
GENERIC MAP (
INIT => X"6000")
PORT MAP (
Z => radmsb,
D => xorrmsb_VCC,
C => xorrmsb_VCC,
B => rad8,
A => rad7);
fullSEQ_xnorremEQ0_inst_0: FADD2
PORT MAP (
S1 => fullSEQ_xnorremEQ0_temp1,
S0 => fullSEQ_xnorremEQ0_temp0,
COUT1 => fullSEQ_xnorremEQ0_temp2,
COUT0 => fEqOut,
CI => fullSEQ_VCC,
B1 => fullSEQ_xnorremEQ0_GND,
B0 => fullSEQ_xnorremEQ0_GND,
A1 => fullSEQ_xnorremEQ0_GND,
A0 => fullSEQ_xnorremEQ0_Int0);
regInst21: FD1S3DX
PORT MAP (
Q => fEqReg01,
CD => Reset,
CK => WrClock,
D => RdAddress1);
fullSEQ_I000000: VHI
PORT MAP (
Z => fullSEQ_VCC);
emptyEQ_xnor4BitEQ0_inst0: ORCALUT4
GENERIC MAP (
INIT => X"9009")
PORT MAP (
Z => emptyEQ_xnor4BitEQ0_Int0,
D => eEqReg11,
C => rCntGBQ1,
B => eEqReg10,
A => rCntGBQ0);
regInst22: FD1S3DX
PORT MAP (
Q => fEqReg11,
CD => Reset,
CK => WrClock,
D => fEqReg01);
einvInst: INV
PORT MAP (
Z => fEqOut1,
A => fEqOut);
RdAddrGen_bufInst0: BUFBA
PORT MAP (
Z => RdAddrGen_BINQ8,
A => rCntQ8);
RdAddrGen_xorGB4_inst1: ORCALUT4
GENERIC MAP (
INIT => X"6000")
PORT MAP (
Z => RdAddrGen_BINQ4,
D => RdAddrGen_xorGB4_VCC,
C => RdAddrGen_xorGB4_VCC,
B => RdAddrGen_BINQ5,
A => RdAddress4);
emptyEQ_xnor4BitEQ0_inst1: ORCALUT4
GENERIC MAP (
INIT => X"9009")
PORT MAP (
Z => emptyEQ_xnor4BitEQ0_Int1,
D => eEqReg13,
C => rCntGBQ3,
B => eEqReg12,
A => rCntGBQ2);
aeSubXor_I000000: VHI
PORT MAP (
Z => aeSubXor_VCC);
WrAddrGen_cAdder_vgbAdderInst1_Adder0: FADD2
PORT MAP (
S1 => wCntNBQ5,
S0 => wCntNBQ4,
COUT1 => WrAddrGen_cAdder_vgbAdderInst1_Cout0,
COUT0 => WrAddrGen_cAdder_vgbAdderInst1_tmp0,
CI => WrAddrGen_cAdder_Cout4,
B1 => WrAddrGen_GND,
B0 => WrAddrGen_GND,
A1 => WrAddrGen_BINQ5,
A0 => WrAddrGen_BINQ4);
regInst23: FD1S3DX
PORT MAP (
Q => fEqReg02,
CD => Reset,
CK => WrClock,
D => RdAddress2);
RdAddrGen_bufInst1: BUFBA
PORT MAP (
Z => rad8,
A => RdAddrGen_NBQ8);
RdAddrGen_xorBG1_inst1: ORCALUT4
GENERIC MAP (
INIT => X"6000")
PORT MAP (
Z => rCntGBQ1,
D => RdAddrGen_xorBG1_VCC,
C => RdAddrGen_xorBG1_VCC,
B => rCntNBQ2,
A => rCntNBQ1);
aeSub_vgbAdderInst2_Sub0: FSUB2
PORT MAP (
S1 => aeSub_vgbAdderInst2_tmp1,
S0 => aeSubOut8,
BOUT1 => aeSub_vgbAdderInst2_tmp0,
BOUT0 => aeSub_Cout,
BI => aeSub_Cout8,
B1 => aeSub_vgbAdderInst2_GND,
B0 => GND,
A1 => aeSub_vgbAdderInst2_GND,
A0 => aeSub8);
WrAddrGen_cAdder_vgbAdderInst1_Adder1: FADD2
PORT MAP (
S1 => wCntNBQ7,
S0 => wCntNBQ6,
COUT1 => WrAddrGen_cAdder_Cout8,
COUT0 => WrAddrGen_cAdder_vgbAdderInst1_tmp1,
CI => WrAddrGen_cAdder_vgbAdderInst1_Cout0,
B1 => WrAddrGen_GND,
B0 => WrAddrGen_GND,
A1 => WrAddrGen_BINQ7,
A0 => WrAddrGen_BINQ6);
WrAddrGen_xorBG1_I000000: VHI
PORT MAP (
Z => WrAddrGen_xorBG1_VCC);
regInst24: FD1S3DX
PORT MAP (
Q => fEqReg12,
CD => Reset,
CK => WrClock,
D => fEqReg02);
fullSEQ_xnorremEQ0_I000000: VLO
PORT MAP (
Z => fullSEQ_xnorremEQ0_GND);
afSubXor4_inst1: ORCALUT4
GENERIC MAP (
INIT => X"6000")
PORT MAP (
Z => afSub4,
D => afSubXor4_VCC,
C => afSubXor4_VCC,
B => afSub5,
A => fEqReg14);
RdAddrGen_xorBG1_I000000: VHI
PORT MAP (
Z => RdAddrGen_xorBG1_VCC);
regInst25: FD1S3DX
PORT MAP (
Q => fEqReg03,
CD => Reset,
CK => WrClock,
D => RdAddress3);
fullSEQ_xnorremEQ0_I000001: VHI
PORT MAP (
Z => fullSEQ_xnorremEQ0_VCC);
xorFEQ_I000000: VHI
PORT MAP (
Z => xorFEQ_VCC);
aeLEInst_I000000: VLO
PORT MAP (
Z => aeLEInst_GND);
aeLEInst_agbInst1: ALEB2
PORT MAP (
LE => aeLEInst_agbOut1,
CI => aeLEInst_agbOut0,
B1 => GND,
B0 => VCC,
A1 => aeSubOut3,
A0 => aeSubOut2);
aeSubXor0_I000000: VHI
PORT MAP (
Z => aeSubXor0_VCC);
WrAddrGen_xorBG3_I000000: VHI
PORT MAP (
Z => WrAddrGen_xorBG3_VCC);
RdAddrGen_xorBG2_I000000: VHI
PORT MAP (
Z => RdAddrGen_xorBG2_VCC);
regInst0: FD1S3DX
PORT MAP (
Q => eEqReg00,
CD => Reset,
CK => RdClock,
D => WrAddress0);
regInst26: FD1S3DX
PORT MAP (
Q => fEqReg13,
CD => Reset,
CK => WrClock,
D => fEqReg03);
regInst31: FD1S3DX
PORT MAP (
Q => fEqReg06,
CD => Reset,
CK => WrClock,
D => RdAddress6);
aeLEInst_I000001: VHI
PORT MAP (
Z => aeLEInst_VCC);
aeLEInst_agbInst2: ALEB2
PORT MAP (
LE => aeLEInst_agbOut2,
CI => aeLEInst_agbOut1,
B1 => GND,
B0 => GND,
A1 => aeSubOut5,
A0 => aeSubOut4);
WrAddrGen_I000000: VLO
PORT MAP (
Z => WrAddrGen_GND);
WrAddrGen_xorGB0_I000000: VHI
PORT MAP (
Z => WrAddrGen_xorGB0_VCC);
WrAddrGen_xorBG4_I000000: VHI
PORT MAP (
Z => WrAddrGen_xorBG4_VCC);
WrAddrGen_xorGB2_inst1: ORCALUT4
GENERIC MAP (
INIT => X"6000")
PORT MAP (
Z => WrAddrGen_BINQ2,
D => WrAddrGen_xorGB2_VCC,
C => WrAddrGen_xorGB2_VCC,
B => WrAddrGen_BINQ3,
A => WrAddress2);
WrAddrGen_xorBG6_inst1: ORCALUT4
GENERIC MAP (
INIT => X"6000")
PORT MAP (
Z => wCntGBQ6,
D => WrAddrGen_xorBG6_VCC,
C => WrAddrGen_xorBG6_VCC,
B => wCntNBQ7,
A => wCntNBQ6);
aeSubXor1_I000000: VHI
PORT MAP (
Z => aeSubXor1_VCC);
aeSubXor3_inst1: ORCALUT4
GENERIC MAP (
INIT => X"6000")
PORT MAP (
Z => aeSub3,
D => aeSubXor3_VCC,
C => aeSubXor3_VCC,
B => aeSub4,
A => eEqReg13);
RdAddrGen_xorBG3_I000000: VHI
PORT MAP (
Z => RdAddrGen_xorBG3_VCC);
RdAddrGen_xorGB1_inst1: ORCALUT4
GENERIC MAP (
INIT => X"6000")
PORT MAP (
Z => RdAddrGen_BINQ1,
D => RdAddrGen_xorGB1_VCC,
C => RdAddrGen_xorGB1_VCC,
B => RdAddrGen_BINQ2,
A => RdAddress1);
RdAddrGen_xorBG5_inst1: ORCALUT4
GENERIC MAP (
INIT => X"6000")
PORT MAP (
Z => rCntGBQ5,
D => RdAddrGen_xorBG5_VCC,
C => RdAddrGen_xorBG5_VCC,
B => rCntNBQ6,
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