📄 rx_cnt_fifo.vhd
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SIGNAL wCntQ8 :std_logic;
SIGNAL wCntNBQ0 :std_logic;
SIGNAL afSubOut4 :std_logic;
SIGNAL rCntNBQ1 :std_logic;
SIGNAL afSubXnor_Int0 :std_logic;
SIGNAL afSubXor1_VCC :std_logic;
SIGNAL wadmsb :std_logic;
SIGNAL rad7 :std_logic;
SIGNAL eEqReg14 :std_logic;
SIGNAL wCntNBQ1 :std_logic;
SIGNAL afSubOut5 :std_logic;
SIGNAL rCntNBQ2 :std_logic;
SIGNAL RdAddrGen_xorBG1_VCC:std_logic;
SIGNAL rad8 :std_logic;
SIGNAL eEqReg15 :std_logic;
SIGNAL wCntNBQ2 :std_logic;
SIGNAL afSubOut6 :std_logic;
SIGNAL rCntNBQ3 :std_logic;
SIGNAL FifoRam_GND :std_logic;
SIGNAL WrAddrGen_cAdder_vgbAdderInst2_GND:std_logic;
SIGNAL RdAddrGen_BINQ0 :std_logic;
SIGNAL wCntNBQ3 :std_logic;
SIGNAL RdAddress0 :std_logic;
SIGNAL eEqReg16 :std_logic;
SIGNAL afSubOut7 :std_logic;
SIGNAL rCntNBQ4 :std_logic;
SIGNAL WrAddrGen_xorGB0_VCC:std_logic;
SIGNAL WrAddrGen_xorBG4_VCC:std_logic;
SIGNAL aeSubXor1_VCC :std_logic;
SIGNAL RdAddrGen_BINQ1 :std_logic;
SIGNAL fullSEQ_xnorremEQ0_Int0:std_logic;
SIGNAL wCntNBQ4 :std_logic;
SIGNAL RdAddress1 :std_logic;
SIGNAL eEqReg17 :std_logic;
SIGNAL afSubOut8 :std_logic;
SIGNAL rCntNBQ5 :std_logic;
SIGNAL WrAddrGen_GND :std_logic;
SIGNAL afSubXor5_VCC :std_logic;
SIGNAL RdAddrGen_BINQ2 :std_logic;
SIGNAL aeSub_vgbAdderInst1_Cout0:std_logic;
SIGNAL wCntNBQ5 :std_logic;
SIGNAL RdAddress2 :std_logic;
SIGNAL eEqReg18 :std_logic;
SIGNAL rCntNBQ6 :std_logic;
SIGNAL RdAddrGen_BINQ3 :std_logic;
SIGNAL RdAddrGen_xorGB1_VCC:std_logic;
SIGNAL RdAddrGen_xorBG5_VCC:std_logic;
SIGNAL afLEInst_agbOut0 :std_logic;
SIGNAL wCntNBQ6 :std_logic;
SIGNAL RdAddress3 :std_logic;
SIGNAL rCntNBQ7 :std_logic;
SIGNAL fullEQ_VCC :std_logic;
SIGNAL RdAddrGen_BINQ4 :std_logic;
SIGNAL afLEInst_agbOut1 :std_logic;
SIGNAL RdAddress4 :std_logic;
SIGNAL wCntNBQ7 :std_logic;
SIGNAL WrAddrGen_cAdder_Cout4:std_logic;
SIGNAL WrAddrGen_xorGB4_VCC:std_logic;
SIGNAL aeSubXor5_VCC :std_logic;
SIGNAL RdAddrGen_BINQ5 :std_logic;
SIGNAL RdAddrGen_cAdder_vgbAdderInst2_tmp0:std_logic;
SIGNAL afLEInst_agbOut2 :std_logic;
SIGNAL RdAddress5 :std_logic;
SIGNAL RdEnOut :std_logic;
SIGNAL emptySEQ_xnorremEQ0_VCC:std_logic;
SIGNAL afSub_vgbAdderInst0_Cout0:std_logic;
SIGNAL RdAddrGen_BINQ6 :std_logic;
SIGNAL RdAddrGen_cAdder_vgbAdderInst2_tmp1:std_logic;
SIGNAL afLEInst_agbOut3 :std_logic;
SIGNAL RdAddress6 :std_logic;
SIGNAL RdAddrGen_BINQ7 :std_logic;
SIGNAL RdAddrGen_xorGB5_VCC:std_logic;
SIGNAL xorEEQ_VCC :std_logic;
SIGNAL aeSub_vgbAdderInst0_tmp0:std_logic;
SIGNAL RdAddress7 :std_logic;
SIGNAL fEqReg10 :std_logic;
SIGNAL WrAddrGen_cAdder_vgbAdderInst2_tmp0:std_logic;
SIGNAL fullEQ_xnor4BitEQ0_temp0:std_logic;
SIGNAL RdAddrGen_BINQ8 :std_logic;
SIGNAL afSubXnor_GND :std_logic;
SIGNAL aeSub_vgbAdderInst0_tmp1:std_logic;
SIGNAL VCC :std_logic;
SIGNAL eAndOut :std_logic;
SIGNAL fEqReg11 :std_logic;
SIGNAL WrAddrGen_cAdder_Cout8:std_logic;
SIGNAL WrAddrGen_cAdder_vgbAdderInst2_tmp1:std_logic;
SIGNAL fullEQ_xnor4BitEQ0_temp1:std_logic;
SIGNAL afSubXnor_temp0 :std_logic;
SIGNAL emptyEQ_xnor4BitEQ0_Int0:std_logic;
SIGNAL fEqReg12 :std_logic;
SIGNAL fullEQ_xnor4BitEQ0_temp2:std_logic;
SIGNAL afSub_vgbAdderInst2_GND:std_logic;
SIGNAL afSubXnor_temp1 :std_logic;
SIGNAL afLEInst_GND :std_logic;
SIGNAL emptyEQ_xnor4BitEQ0_Int1:std_logic;
SIGNAL fEqReg13 :std_logic;
SIGNAL afSubXnor_temp2 :std_logic;
SIGNAL aeSub_vgbAdderInst2_Cout0:std_logic;
SIGNAL fEqReg14 :std_logic;
SIGNAL WrAddrGen_cAdder_vgbAdderInst0_Cout0:std_logic;
SIGNAL aeSubXor_VCC :std_logic;
SIGNAL fEqReg15 :std_logic;
SIGNAL afSubXor0_VCC :std_logic;
SIGNAL fEqReg16 :std_logic;
SIGNAL RdAddrGen_xorBG0_VCC:std_logic;
SIGNAL fEqReg17 :std_logic;
SIGNAL afSub_vgbAdderInst1_Cout0:std_logic;
SIGNAL fullSEQ_xnorremEQ0_GND:std_logic;
SIGNAL wad7 :std_logic;
SIGNAL fEqReg18 :std_logic;
SIGNAL xorFEQ_VCC :std_logic;
SIGNAL aeSubXor0_VCC :std_logic;
SIGNAL WrAddrGen_xorBG3_VCC:std_logic;
SIGNAL emptySEQ_xnorremEQ0_temp0:std_logic;
SIGNAL fullEQ_xnor4BitEQ1_GND:std_logic;
SIGNAL afSub_vgbAdderInst0_tmp0:std_logic;
SIGNAL fullEQ_xnor4BitEQ0_Int0:std_logic;
SIGNAL wad8 :std_logic;
SIGNAL aeLEInst_GND :std_logic;
SIGNAL afSubXor4_VCC :std_logic;
SIGNAL emptySEQ_xnorremEQ0_temp1:std_logic;
SIGNAL fullEQ_xnor4BitEQ1_temp0:std_logic;
SIGNAL afSub_vgbAdderInst0_tmp1:std_logic;
SIGNAL fullEQ_xnor4BitEQ0_Int1:std_logic;
SIGNAL fAndOut :std_logic;
SIGNAL emptySEQ_xnorremEQ0_temp2:std_logic;
SIGNAL fullEQ_xnor4BitEQ1_temp1:std_logic;
SIGNAL RdAddrGen_xorGB0_VCC:std_logic;
SIGNAL RdAddrGen_xorBG4_VCC:std_logic;
SIGNAL aeSub_Cout :std_logic;
SIGNAL fullEQ_xnor4BitEQ1_temp2:std_logic;
SIGNAL emptyEQ_Cout0 :std_logic;
SIGNAL rCntQ7 :std_logic;
SIGNAL aeLEOut :std_logic;
SIGNAL WrAddrGen_xorGB3_VCC:std_logic;
SIGNAL WrAddrGen_xorBG7_VCC:std_logic;
SIGNAL aeSubXor4_VCC :std_logic;
SIGNAL rCntQ8 :std_logic;
SIGNAL WrAddrGen_cAdder_vgbAdderInst1_Cout0:std_logic;
SIGNAL radmsb :std_logic;
SIGNAL eEqReg00 :std_logic;
SIGNAL RdAddrGen_xorGB4_VCC:std_logic;
SIGNAL eEqReg01 :std_logic;
SIGNAL RdAddrGen_GND :std_logic;
SIGNAL eEqReg02 :std_logic;
SIGNAL WrAddrGen_xorGB7_VCC:std_logic;
SIGNAL afSub_vgbAdderInst2_Cout0:std_logic;
SIGNAL WrEnOut :std_logic;
SIGNAL eEqReg03 :std_logic;
SIGNAL eEqReg04 :std_logic;
SIGNAL afSub0 :std_logic;
SIGNAL aeLEInst_agbOut0 :std_logic;
SIGNAL eEqReg05 :std_logic;
SIGNAL afSub1 :std_logic;
SIGNAL aeLEInst_agbOut1 :std_logic;
SIGNAL RdAddrGen_cAdder_vgbAdderInst0_tmp0:std_logic;
SIGNAL eandbInst_VCC :std_logic;
SIGNAL RdAddrGen_cAdder_vgbAdderInst0_tmp1:std_logic;
SIGNAL eEqReg06 :std_logic;
SIGNAL eEqOut0 :std_logic;
SIGNAL afSub2 :std_logic;
SIGNAL aeLEInst_agbOut2 :std_logic;
SIGNAL aeSub_vgbAdderInst1_tmp0:std_logic;
SIGNAL emptyEQ_VCC :std_logic;
SIGNAL RdAddrGen_cAdder_vgbAdderInst0_Cout0:std_logic;
SIGNAL eEqReg07 :std_logic;
SIGNAL eEqOut1 :std_logic;
SIGNAL afSub3 :std_logic;
SIGNAL aeLEInst_agbOut3 :std_logic;
SIGNAL aeSub_vgbAdderInst1_tmp1:std_logic;
SIGNAL eEqReg08 :std_logic;
SIGNAL afSub4 :std_logic;
SIGNAL WrAddrGen_NBQ8 :std_logic;
SIGNAL WrAddrGen_cAdder_vgbAdderInst0_tmp0:std_logic;
SIGNAL emptyEQ_xnor4BitEQ1_Int0:std_logic;
SIGNAL fullEQ_xnor4BitEQ0_GND:std_logic;
SIGNAL afSub5 :std_logic;
SIGNAL WrAddrGen_cAdder_vgbAdderInst0_tmp1:std_logic;
SIGNAL WrAddrGen_xorBG2_VCC:std_logic;
SIGNAL emptyEQ_xnor4BitEQ1_Int1:std_logic;
SIGNAL afSub6 :std_logic;
SIGNAL afSubXor3_VCC :std_logic;
SIGNAL emptyEQ_xnor4BitEQ0_temp0:std_logic;
SIGNAL RdAddrGen_xorBG3_VCC:std_logic;
SIGNAL emptyEQ_xnor4BitEQ0_temp1:std_logic;
SIGNAL eEqmsb :std_logic;
SIGNAL afSub8 :std_logic;
SIGNAL emptyEQ_xnor4BitEQ0_temp2:std_logic;
SIGNAL fEqReg00 :std_logic;
SIGNAL WrAddrGen_xorGB2_VCC:std_logic;
SIGNAL WrAddrGen_xorBG6_VCC:std_logic;
SIGNAL aeSubXor3_VCC :std_logic;
SIGNAL xorrmsb_VCC :std_logic;
SIGNAL fEqReg01 :std_logic;
SIGNAL afSub_vgbAdderInst1_tmp0:std_logic;
SIGNAL fEqReg02 :std_logic;
SIGNAL fEqOut0 :std_logic;
SIGNAL fEqOut :std_logic;
SIGNAL xorwmsb_VCC :std_logic;
SIGNAL RdAddrGen_xorGB3_VCC:std_logic;
SIGNAL RdAddrGen_xorBG7_VCC:std_logic;
SIGNAL fullEQ_xnor4BitEQ1_Int0:std_logic;
SIGNAL fEqReg03 :std_logic;
SIGNAL fEqOut1 :std_logic;
SIGNAL afSub_vgbAdderInst1_tmp1:std_logic;
SIGNAL RdAddrGen_cAdder_vgbAdderInst1_Cout0:std_logic;
SIGNAL fullEQ_xnor4BitEQ1_Int1:std_logic;
SIGNAL fEqReg04 :std_logic;
SIGNAL WrAddrGen_xorGB6_VCC:std_logic;
SIGNAL emptySEQ_xnorremEQ0_GND:std_logic;
SIGNAL RdAddrGen_NBQ8 :std_logic;
SIGNAL aeSub_VCC :std_logic;
SIGNAL WrAddress0 :std_logic;
SIGNAL fEqReg05 :std_logic;
SIGNAL emptyEQ_xnor4BitEQ1_GND:std_logic;
SIGNAL afLEOut :std_logic;
SIGNAL WrAddress1 :std_logic;
SIGNAL fEqReg06 :std_logic;
SIGNAL aeSub0 :std_logic;
SIGNAL RdAddrGen_xorGB7_VCC:std_logic;
SIGNAL afLEInst_VCC :std_logic;
SIGNAL emptyEQ_xnor4BitEQ1_temp0:std_logic;
SIGNAL GND :std_logic;
SIGNAL WrAddress2 :std_logic;
SIGNAL fEqReg07 :std_logic;
SIGNAL aeSub1 :std_logic;
SIGNAL aeSub_Cout4 :std_logic;
SIGNAL emptyEQ_xnor4BitEQ1_temp1:std_logic;
SIGNAL WrAddress3 :std_logic;
SIGNAL fEqReg08 :std_logic;
SIGNAL aeSub2 :std_logic;
SIGNAL emptyEQ_xnor4BitEQ1_temp2:std_logic;
SIGNAL fandbInst_VCC :std_logic;
SIGNAL WrAddress4 :std_logic;
SIGNAL aeSub3 :std_logic;
SIGNAL WrAddress5 :std_logic;
SIGNAL aeSubOut0 :std_logic;
SIGNAL aeSub4 :std_logic;
SIGNAL RdAddrGen_cAdder_Cout4:std_logic;
SIGNAL WrAddress6 :std_logic;
SIGNAL aeSubOut1 :std_logic;
SIGNAL aeSub5 :std_logic;
SIGNAL WrAddrGen_xorBG1_VCC:std_logic;
SIGNAL aeSub_Cout8 :std_logic;
SIGNAL fullSEQ_xnorremEQ0_VCC:std_logic;
SIGNAL afSub_Cout4 :std_logic;
SIGNAL WrAddress7 :std_logic;
SIGNAL aeSubOut2 :std_logic;
SIGNAL aeSub6 :std_logic;
SIGNAL afSubXor2_VCC :std_logic;
SIGNAL aeSubOut3 :std_logic;
SIGNAL aeLEInst_VCC :std_logic;
SIGNAL RdAddrGen_cAdder_vgbAdderInst1_tmp0:std_logic;
SIGNAL RdAddrGen_xorBG2_VCC:std_logic;
SIGNAL Full_sig : std_logic;
SIGNAL Empty_sig : std_logic;
BEGIN
Full <= Full_sig;
Empty <= Empty_sig;
regInst13: FD1S3DX
PORT MAP (
Q => eEqReg16,
CD => Reset,
CK => RdClock,
D => eEqReg06);
WrAddrGen_xorGB1_inst1: ORCALUT4
GENERIC MAP (
INIT => X"6000")
PORT MAP (
Z => WrAddrGen_BINQ1,
D => WrAddrGen_xorGB1_VCC,
C => WrAddrGen_xorGB1_VCC,
B => WrAddrGen_BINQ2,
A => WrAddress1);
WrAddrGen_xorBG5_inst1: ORCALUT4
GENERIC MAP (
INIT => X"6000")
PORT MAP (
Z => wCntGBQ5,
D => WrAddrGen_xorBG5_VCC,
C => WrAddrGen_xorBG5_VCC,
B => wCntNBQ6,
A => wCntNBQ5);
aeSubXor2_inst1: ORCALUT4
GENERIC MAP (
INIT => X"6000")
PORT MAP (
Z => aeSub2,
D => aeSubXor2_VCC,
C => aeSubXor2_VCC,
B => aeSub3,
A => eEqReg12);
RdAddrGen_xorGB0_inst1: ORCALUT4
GENERIC MAP (
INIT => X"6000")
PORT MAP (
Z => RdAddrGen_BINQ0,
D => RdAddrGen_xorGB0_VCC,
C => RdAddrGen_xorGB0_VCC,
B => RdAddrGen_BINQ1,
A => RdAddress0);
RdAddrGen_xorBG4_inst1: ORCALUT4
GENERIC MAP (
INIT => X"6000")
PORT MAP (
Z => rCntGBQ4,
D => RdAddrGen_xorBG4_VCC,
C => RdAddrGen_xorBG4_VCC,
B => rCntNBQ5,
A => rCntNBQ4);
regInst14: FD1S3DX
PORT MAP (
Q => eEqReg07,
CD => Reset,
CK => RdClock,
D => wCntQ7);
eandbInst_inst1: ORCALUT4
GENERIC MAP (
INIT => X"4000")
PORT MAP (
Z => RdEnOut,
D => eandbInst_VCC,
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