📄 rx_cnt_fifo.vhd
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--VHDL netlist generated by scuba
--timeStamp 2005 4 25 20 23 54
USE STD.TEXTIO.ALL;
Library IEEE, EC;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE EC.COMPONENTS.ALL;
USE WORK.ALL;
ENTITY RX_CNT_FIFO IS
PORT (
Data :IN std_logic_vector(7 downto 0);
WrClock :IN std_logic;
RdClock :IN std_logic;
WrEn :IN std_logic;
RdEn :IN std_logic;
Reset :IN std_logic;
Q :OUT std_logic_vector(7 downto 0);
Full :OUT std_logic;
AlmostFull :OUT std_logic;
Empty :OUT std_logic;
AlmostEmpty :OUT std_logic);
END RX_CNT_FIFO;
ARCHITECTURE V OF RX_CNT_FIFO IS
COMPONENT FD1S3DX
PORT (
D :IN std_logic;
CK :IN std_logic;
CD :IN std_logic;
Q :OUT std_logic);
END COMPONENT;
COMPONENT ORCALUT4
GENERIC (
INIT : BIT_VECTOR);
PORT (
A :IN std_logic;
B :IN std_logic;
C :IN std_logic;
D :IN std_logic;
Z :OUT std_logic);
END COMPONENT;
COMPONENT FADD2
PORT (
A0 :IN std_logic;
A1 :IN std_logic;
B0 :IN std_logic;
B1 :IN std_logic;
CI :IN std_logic;
COUT0 :OUT std_logic;
COUT1 :OUT std_logic;
S0 :OUT std_logic;
S1 :OUT std_logic);
END COMPONENT;
COMPONENT VHI
PORT (
Z :OUT std_logic);
END COMPONENT;
COMPONENT INV
PORT (
A :IN std_logic;
Z :OUT std_logic);
END COMPONENT;
COMPONENT BUFBA
PORT (
A :IN std_logic;
Z :OUT std_logic);
END COMPONENT;
COMPONENT FSUB2
PORT (
A0 :IN std_logic;
A1 :IN std_logic;
B0 :IN std_logic;
B1 :IN std_logic;
BI :IN std_logic;
BOUT0 :OUT std_logic;
BOUT1 :OUT std_logic;
S0 :OUT std_logic;
S1 :OUT std_logic);
END COMPONENT;
COMPONENT VLO
PORT (
Z :OUT std_logic);
END COMPONENT;
COMPONENT ALEB2
PORT (
A0 :IN std_logic;
A1 :IN std_logic;
B0 :IN std_logic;
B1 :IN std_logic;
CI :IN std_logic;
LE :OUT std_logic);
END COMPONENT;
COMPONENT FD1S3BX
PORT (
D :IN std_logic;
CK :IN std_logic;
PD :IN std_logic;
Q :OUT std_logic);
END COMPONENT;
COMPONENT AND2
PORT (
A :IN std_logic;
B :IN std_logic;
Z :OUT std_logic);
END COMPONENT;
COMPONENT PDP8KA
GENERIC (
DATA_WIDTH_W : integer := 9;
DATA_WIDTH_R : integer := 9;
CSDECODE_R : string := "000";
CSDECODE_W : string := "000";
INITVAL_00 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_01 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_02 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_03 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_04 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_05 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_06 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_07 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_08 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_09 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_0A : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_0B : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_0C : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_0D : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_0E : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_0F : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_10 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_11 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_12 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_13 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_14 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_15 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_16 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_17 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_18 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_19 : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_1A : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_1B : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_1C : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_1D : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_1E : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INITVAL_1F : string := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
GSR : string := "DISABLED";
RESETMODE : string := "ASYNC");
PORT (
CEW :IN std_logic;
CLKW :IN std_logic;
CSW0 :IN std_logic;
CSW1 :IN std_logic;
CSW2 :IN std_logic;
WE :IN std_logic;
CER :IN std_logic;
CLKR :IN std_logic;
CSR0 :IN std_logic;
CSR1 :IN std_logic;
CSR2 :IN std_logic;
RST :IN std_logic;
DI0 :IN std_logic;
DI1 :IN std_logic;
DI2 :IN std_logic;
DI3 :IN std_logic;
DI4 :IN std_logic;
DI5 :IN std_logic;
DI6 :IN std_logic;
DI7 :IN std_logic;
DI8 :IN std_logic;
DI9 :IN std_logic;
DI10 :IN std_logic;
DI11 :IN std_logic;
DI12 :IN std_logic;
DI13 :IN std_logic;
DI14 :IN std_logic;
DI15 :IN std_logic;
DI16 :IN std_logic;
DI17 :IN std_logic;
DI18 :IN std_logic;
DI19 :IN std_logic;
DI20 :IN std_logic;
DI21 :IN std_logic;
DI22 :IN std_logic;
DI23 :IN std_logic;
DI24 :IN std_logic;
DI25 :IN std_logic;
DI26 :IN std_logic;
DI27 :IN std_logic;
DI28 :IN std_logic;
DI29 :IN std_logic;
DI30 :IN std_logic;
DI31 :IN std_logic;
DI32 :IN std_logic;
DI33 :IN std_logic;
DI34 :IN std_logic;
DI35 :IN std_logic;
ADW0 :IN std_logic;
ADW1 :IN std_logic;
ADW2 :IN std_logic;
ADW3 :IN std_logic;
ADW4 :IN std_logic;
ADW5 :IN std_logic;
ADW6 :IN std_logic;
ADW7 :IN std_logic;
ADW8 :IN std_logic;
ADW9 :IN std_logic;
ADW10 :IN std_logic;
ADW11 :IN std_logic;
ADW12 :IN std_logic;
ADR0 :IN std_logic;
ADR1 :IN std_logic;
ADR2 :IN std_logic;
ADR3 :IN std_logic;
ADR4 :IN std_logic;
ADR5 :IN std_logic;
ADR6 :IN std_logic;
ADR7 :IN std_logic;
ADR8 :IN std_logic;
ADR9 :IN std_logic;
ADR10 :IN std_logic;
ADR11 :IN std_logic;
ADR12 :IN std_logic;
DO0 :OUT std_logic;
DO1 :OUT std_logic;
DO2 :OUT std_logic;
DO3 :OUT std_logic;
DO4 :OUT std_logic;
DO5 :OUT std_logic;
DO6 :OUT std_logic;
DO7 :OUT std_logic;
DO8 :OUT std_logic;
DO9 :OUT std_logic;
DO10 :OUT std_logic;
DO11 :OUT std_logic;
DO12 :OUT std_logic;
DO13 :OUT std_logic;
DO14 :OUT std_logic;
DO15 :OUT std_logic;
DO16 :OUT std_logic;
DO17 :OUT std_logic;
DO18 :OUT std_logic;
DO19 :OUT std_logic;
DO20 :OUT std_logic;
DO21 :OUT std_logic;
DO22 :OUT std_logic;
DO23 :OUT std_logic;
DO24 :OUT std_logic;
DO25 :OUT std_logic;
DO26 :OUT std_logic;
DO27 :OUT std_logic;
DO28 :OUT std_logic;
DO29 :OUT std_logic;
DO30 :OUT std_logic;
DO31 :OUT std_logic;
DO32 :OUT std_logic;
DO33 :OUT std_logic;
DO34 :OUT std_logic;
DO35 :OUT std_logic);
END COMPONENT;
SIGNAL aeSubOut4 :std_logic;
SIGNAL aeSub8 :std_logic;
SIGNAL RdAddrGen_cAdder_vgbAdderInst1_tmp1:std_logic;
SIGNAL aeSub_vgbAdderInst2_tmp0:std_logic;
SIGNAL rCntGBQ0 :std_logic;
SIGNAL aeSubOut5 :std_logic;
SIGNAL WrAddrGen_xorGB1_VCC:std_logic;
SIGNAL WrAddrGen_xorBG5_VCC:std_logic;
SIGNAL aeSubXor2_VCC :std_logic;
SIGNAL RdAddrGen_cAdder_Cout8:std_logic;
SIGNAL aeSub_vgbAdderInst2_tmp1:std_logic;
SIGNAL rCntGBQ1 :std_logic;
SIGNAL wCntGBQ0 :std_logic;
SIGNAL aeSubOut6 :std_logic;
SIGNAL WrAddrGen_BINQ0 :std_logic;
SIGNAL WrAddrGen_cAdder_vgbAdderInst1_tmp0:std_logic;
SIGNAL emptySEQ_VCC :std_logic;
SIGNAL afSubXor6_VCC :std_logic;
SIGNAL afSub_Cout :std_logic;
SIGNAL afSub_Cout8 :std_logic;
SIGNAL rCntGBQ2 :std_logic;
SIGNAL wCntGBQ1 :std_logic;
SIGNAL aeSubOut7 :std_logic;
SIGNAL WrAddrGen_BINQ1 :std_logic;
SIGNAL WrAddrGen_cAdder_vgbAdderInst1_tmp1:std_logic;
SIGNAL afSub_VCC :std_logic;
SIGNAL RdAddrGen_xorGB2_VCC:std_logic;
SIGNAL RdAddrGen_xorBG6_VCC:std_logic;
SIGNAL rCntGBQ3 :std_logic;
SIGNAL wCntGBQ2 :std_logic;
SIGNAL aeSubOut8 :std_logic;
SIGNAL WrAddrGen_BINQ2 :std_logic;
SIGNAL aeSub_vgbAdderInst2_GND:std_logic;
SIGNAL rCntGBQ4 :std_logic;
SIGNAL wCntGBQ3 :std_logic;
SIGNAL WrAddrGen_BINQ3 :std_logic;
SIGNAL WrAddrGen_xorGB5_VCC:std_logic;
SIGNAL aeSubXor6_VCC :std_logic;
SIGNAL rCntGBQ5 :std_logic;
SIGNAL wCntGBQ4 :std_logic;
SIGNAL fEqmsb :std_logic;
SIGNAL WrAddrGen_BINQ4 :std_logic;
SIGNAL emptyEQ_xnor4BitEQ0_GND:std_logic;
SIGNAL rCntGBQ6 :std_logic;
SIGNAL wCntGBQ5 :std_logic;
SIGNAL WrAddrGen_BINQ5 :std_logic;
SIGNAL RdAddrGen_xorGB6_VCC:std_logic;
SIGNAL fullSEQ_xnorremEQ0_temp0:std_logic;
SIGNAL wCntGBQ6 :std_logic;
SIGNAL WrAddrGen_BINQ6 :std_logic;
SIGNAL emptySEQ_xnorremEQ0_Int0:std_logic;
SIGNAL RdAddrGen_cAdder_vgbAdderInst2_GND:std_logic;
SIGNAL aeSub_vgbAdderInst0_Cout0:std_logic;
SIGNAL fullSEQ_xnorremEQ0_temp1:std_logic;
SIGNAL afSubOut0 :std_logic;
SIGNAL WrAddrGen_BINQ7 :std_logic;
SIGNAL afSub_vgbAdderInst2_tmp0:std_logic;
SIGNAL fullSEQ_xnorremEQ0_temp2:std_logic;
SIGNAL eEqReg10 :std_logic;
SIGNAL afSubOut1 :std_logic;
SIGNAL WrAddrGen_BINQ8 :std_logic;
SIGNAL fullEQ_Cout0 :std_logic;
SIGNAL afSub_vgbAdderInst2_tmp1:std_logic;
SIGNAL fullSEQ_VCC :std_logic;
SIGNAL eEqReg11 :std_logic;
SIGNAL afSubOut2 :std_logic;
SIGNAL eEqReg12 :std_logic;
SIGNAL wCntQ7 :std_logic;
SIGNAL afSubOut3 :std_logic;
SIGNAL rCntNBQ0 :std_logic;
SIGNAL WrAddrGen_xorBG0_VCC:std_logic;
SIGNAL eEqReg13 :std_logic;
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