sc_hdlc.vhd

在通讯领域中使用相当广泛的HDLC

-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2005 by Lattice Semiconductor Corporation
-- --------------------------------------------------------------------
--  Project:           Single-Channel HDLC
--  File:              SC_HDLC.vhd
--  Title:             SC_HDLC
--  Design Library:    IEEE
--  Dependencies:      IEEE.std_logic_1164.all
--                     IEEE.std_logic_unsigned.all
--  Description:       Top VHDL file for the Single Channel-HDLC design
--
-- --------------------------------------------------------------------
--
-- Revision History :
-- --------------------------------------------------------------------
--
-- Revision 1.0  2005-04-12 12:03:46-08  James Lee
-- Initial revision
--
-- --------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_Unsigned.all;

entity SC_HDLC is
  port (
    -- Global Reset
    RST            : in  std_logic; -- Master reset
    
    -- CPU Interface
    CPU_Data_in      : inout  std_logic_vector(7 downto 0); -- CPU input data
    CPU_Data_out     : inout  std_logic_vector(7 downto 0); -- CPU output data
    CPU_Add	     : in  std_logic_vector(2 downto 0);    -- CPU address
    CPU_WRn	     : in  std_logic;                       -- CPU Write/Read enable, When low, Write active
    CPU_DSn          : in  std_logic;			    -- CPU Data Strobe, active low
    CPU_WR_DSn	     : in  std_logic;
    CPU_CS	     : in  std_logic;                       -- CPU Chip selection
    CPU_INTn	     : out std_logic;  			    -- CPU Interrupt
    CPU_clk	     : in  std_logic;			    -- CPU clock
    -- HDLC Receive Serial Interface
    RxClk            : in  std_logic; -- Receive Serial Clock
    RxData           : in  std_logic; -- Receive Serial Data

    -- HDLC Transmit Serial Interface
    TxClk            : in  std_logic; -- Transmit Serial Clock
    TxData           : out std_logic);

 

  
end SC_HDLC;

architecture SC_HDLC_a of SC_HDLC is

COMPONENT TX_FIFO 
        PORT (
        Data                :IN    std_logic_vector(7 downto 0);
        WrClock             :IN    std_logic;
        RdClock             :IN    std_logic;
        WrEn                :IN    std_logic;
        RdEn                :IN    std_logic;
        Reset               :IN    std_logic;
        Q                   :OUT   std_logic_vector(7 downto 0);
        Full                :OUT   std_logic;
        AlmostFull          :OUT   std_logic;
        Empty               :OUT   std_logic;
        AlmostEmpty         :OUT   std_logic);
END COMPONENT;

COMPONENT RX_FIFO 
        PORT (
        Data                :IN    std_logic_vector(7 downto 0);
        WrClock             :IN    std_logic;
        RdClock             :IN    std_logic;
        WrEn                :IN    std_logic;
        RdEn                :IN    std_logic;
        Reset               :IN    std_logic;
        Q                   :OUT   std_logic_vector(7 downto 0);
        Full                :OUT   std_logic;
        AlmostFull          :OUT   std_logic;
        Empty               :OUT   std_logic;
        AlmostEmpty         :OUT   std_logic);
END COMPONENT;

COMPONENT RX_CNT_FIFO 
        PORT (
        Data                :IN    std_logic_vector(7 downto 0);
        WrClock             :IN    std_logic;
        RdClock             :IN    std_logic;
        WrEn                :IN    std_logic;
        RdEn                :IN    std_logic;
        Reset               :IN    std_logic;
        Q                   :OUT   std_logic_vector(7 downto 0);
        Full                :OUT   std_logic;
        AlmostFull          :OUT   std_logic;
        Empty               :OUT   std_logic;
        AlmostEmpty         :OUT   std_logic);
END COMPONENT;

  COMPONENT HDLC_RECEIVE_CCITT
  port (
    -- Global Reset
    Reset  : in  std_logic; -- Master reset
    -- HDLC Receive Serial Interface
    RxC : in  std_logic; -- Receive Serial Clock
    RxD : in  std_logic; -- Receive Serial Data
    -- HDLC Receive External Memory Interface
    RxOutputData_B0 : out std_logic; -- Receive Data Output Bit 0
    RxOutputData_B1 : out std_logic; -- Receive Data Output Bit 1
    RxOutputData_B2 : out std_logic; -- Receive Data Output Bit 2
    RxOutputData_B3 : out std_logic; -- Receive Data Output Bit 3
    RxOutputData_B4 : out std_logic; -- Receive Data Output Bit 4
    RxOutputData_B5 : out std_logic; -- Receive Data Output Bit 5
    RxOutputData_B6 : out std_logic; -- Receive Data Output Bit 6
    RxOutputData_B7 : out std_logic; -- Receive Data Output Bit 7
    RxDataWrite_n   : out std_logic; -- Receive Data Valid
    RxStatusWrite_n : out std_logic; -- Receive Status Valid
    RxEnable        : in  std_logic  -- Receive Enable
  );
  end COMPONENT;

  COMPONENT HDLC_TRANSMIT_CCITT
  port (
    -- Global Reset
    Reset          : in  std_logic; -- Master reset
    -- HDLC Transmit Serial Interface
    TxC            : in  std_logic; -- Transmit Serial Clock
    TxD            : out std_logic; -- Transmit Serial Data
    -- HDLC Transmit External Memory Interface
    TxInputData_B0 : in  std_logic; -- Transmit Data Input Bit 0
    TxInputData_B1 : in  std_logic; -- Transmit Data Input Bit 1
    TxInputData_B2 : in  std_logic; -- Transmit Data Input Bit 2
    TxInputData_B3 : in  std_logic; -- Transmit Data Input Bit 3
    TxInputData_B4 : in  std_logic; -- Transmit Data Input Bit 4
    TxInputData_B5 : in  std_logic; -- Transmit Data Input Bit 5
    TxInputData_B6 : in  std_logic; -- Transmit Data Input Bit 6
    TxInputData_B7 : in  std_logic; -- Transmit Data Input Bit 7
    TxRead_n       : out std_logic; -- Transmit Data Read
    TxEmpty_n      : in  std_logic; -- Transmit Data Empty
    TxStart        : in  std_logic; -- Transmit Start
    TxAbort        : in  std_logic; -- Transmit Abort
    TxEnable       : in  std_logic  -- Transmit Enable
  );
  end COMPONENT;

  attribute syn_black_box : boolean;
  attribute syn_black_box of HDLC_RECEIVE_CCITT: component is true;
  attribute syn_black_box of HDLC_TRANSMIT_CCITT: component is true;


  -- HDLC Receive signal
  signal RxOutputData     :  std_logic_vector(7 downto 0);
  signal RxDataWrite_n    :  std_logic;
  signal RxStatusWrite_n  :  std_logic;
  
  -- HDLC Transmit signal
  signal TxInputData      :  std_logic_vector(7 downto 0);
  signal TxRead_n         :  std_logic;
  signal TxEmpty_n        :  std_logic;
  signal TxStart          :  std_logic;  
  signal TxAbort          :  std_logic;  
  
  type   states is (idle, start, end_frame);
  signal state_status     : states;
  signal bit_cnt          : std_logic_vector(3 downto 0);
  signal byte_cnt         : std_logic_vector(7 downto 0);
  signal frame_cnt        : std_logic_vector(7 downto 0);
  signal Int_32bytes      : std_logic;
  signal Int_End_frame    : std_logic;
  
  signal CRC_ERR          : std_logic;
  signal Octet_ERR        : std_logic;
  signal Abort_DET        : std_logic;
  signal Sig_32B_frame    : std_logic;
  signal Sig_end_Frame    : std_logic;

  signal Rx_Fifo_FF, Rx_Fifo_EF, Rx_Fifo_AFF, Rx_Fifo_AEF : std_logic;
  signal Tx_Fifo_FF, Tx_Fifo_EF, Tx_Fifo_AFF, Tx_Fifo_AEF : std_logic;
  signal Rx_cnt_Fifo_FF, Rx_cnt_Fifo_EF, Rx_cnt_Fifo_AFF, Rx_cnt_Fifo_AEF : std_logic;
  signal RX_SR2           : std_logic_vector(7 downto 0);
  signal TX_Cntl_REG      : std_logic_vector(7 downto 0);
  signal TX_Byte_CNT      : std_logic_vector(7 downto 0);
  signal TX_CPU_DATA      : std_logic_vector(7 downto 0);
  signal Tx_Fifo_WRn, Tx_Fifo_WR, Tx_fifo_RD 	  : std_logic;
  signal Rx_Fifo_RDn, Rx_Fifo_WR	  : std_logic;
  signal Tx_End_sig	  : std_logic;
  signal Low_0, High_1, Inv_RST    : std_logic;
  signal TX_FIFO_valid, RX_FIFO_valid, RX_CNT_FIFO_valid : std_logic;
  signal RX_FIFO_RDEN : std_logic;
  signal Rx_FIFO_rclk : std_logic;
  
  signal    RxDataa           : std_logic; -- Receive Serial Data

  signal    TxDataa           : std_logic;  -- Transmit Serial Data
  signal    Read_clr	   : std_logic;

  signal Rx_FIFO_RST, Rx_MEM_RST, Tx_FIFO_RST, TX_MEM_RST : std_logic;
  signal Rx_cnt_FIFO_RST, Rx_cnt_MEM_RST, Rx_cnt_fifo_wren, Rx_cnt_fifo_rden: std_logic;
  signal Int_tog_end, Int_tog_32, Int_clr_end, Int_clr_32, Intn_end, Intn_32 : std_logic;
  signal Rx_sel : std_logic;
  signal WR_RD_test        : std_logic_vector(7 downto 0);
  signal Int_latch0, Int_latch1, Int_latch2 : std_logic;
  signal rx_cnt_fifo_rden_n : std_logic;
  signal tx_delay, tx_delay1, tx_delay2 : std_logic;
  signal txstart_1, txstart_2, txstart_3 : std_logic;
  signal Int_Clr_end_d : std_logic_vector(9 downto 0);
  signal txcnt_clear_d : std_logic_vector(9 downto 0);
  signal txcnt_clear : std_logic;
  signal rx_cnt_data : std_logic_vector(7 downto 0);
  signal over_256 : std_logic;
  
  
  
  signal diag_cnt : integer range 0 to 500;
  signal rx_reset, rx_error, Rx_HDLC_RST : std_logic;

begin

--****************************** Addresss Map *********************************

--============================== Address "000" ================================
--  WRITE :      Tx FIFO memory Write
--  READ  :      Tx byte count register
--=============================================================================

--============================== Address "001" ================================
--  WRITE only
--  Data1 is high, Tx End frame 
--  Rest bits are not used
--=============================================================================

--============================== Address "010" ================================
-- READ only
--                        Rx Status Register                                 --
--===========================================================================--
--=|  bit7  |  bit6  |  bit5  |  bit4  |  bit3  |  bit2  |  bit1  |  bit0  |=--
--=|========|========|========|========|========|========|========|========|=--
--=| End_FR |   0    |   0    |   0    |    0   |Abor_DET|Oct_ERR |CRC_ERR |=--
--===========================================================================--

--============================== Address "011" ================================
-- READ Only
--                 FIFO Memory available Register                            --
--===========================================================================--
--=|  bit7  |  bit6  |  bit5  |  bit4  |  bit3  |  bit2  |  bit1  |  bit0  |=--
--=|========|========|========|========|========|========|========|========|=--
--=|   0    |   0    |   0    | Tx_FIFO|   0    |   0    |Rx_C_FF |Rx_FIFO |=--
--===========================================================================--

--============================== Address "100" ================================
--  READ only
--  Rx packet byte count register  & Read&Clear function                        
--  If read this register, Interrupt & Rx status register is clear
--  When size of packet is over 256 byte, cpu should read FIFO two times.
--=============================================================================

--============================== Address "101" ================================
-- READ only
-- Rx packet data read
--=============================================================================

--============================== Address "110" ================================
-- Write and Read 
--                   Tx and Rx FIRO Reset Register                           --
--===========================================================================--
--=|  bit7  |  bit6  |  bit5  |  bit4  |  bit3  |  bit2  |  bit1  |  bit0  |=--
--=|========|========|========|========|========|========|========|========|=--
--=|   x    |   x    |   x    |   x    | Rx_sel |Tx_FIFOR|Rx_cntFF|Rx_FIFO |=--
--===========================================================================--


--============================== Address "111" ================================
-- WRITE & READ
-- CPU Write and Read test Register
--=============================================================================



Inv_RST <= not RST;

TxData <= Txdataa;

-- =====================  RxData select ====================================
	process(RST, Rx_sel)     
	  begin
	  	if(RST = '0')then
	  		RxDataa <= Rxdata;
	  	else
			if Rx_sel = '0' then
				Rxdataa <= Txdataa;
			else
				Rxdataa <= Rxdata;
			end if;
		end if;
	  end process;
--==========================================================================



--=========== Reset of Tx and Rx FIFO memory ======
TX_MEM_RST <= not(RST and Tx_FIFO_RST);
RX_MEM_RST <= not(RST and Rx_FIFO_RST and Rx_reset);
RX_CNT_MEM_RST <= not(RST and Rx_CNT_FIFO_RST and Rx_reset);

Rx_HDLC_RST <= not (RST and Rx_reset);

--=================================================

--==================== Rx HDLC Controller ============================
  RX: HDLC_RECEIVE_CCITT port map(
    -- Global Reset
    Reset           => Rx_HDLC_RST,              -- Master reset
    -- HDLC Receive Serial Interface
    RxC             => RxClk,              -- Receive Serial Clock
    RxD             => RxDataa,             -- Receive Serial Data
    -- HDLC Receive External Memory Interface
    RxOutputData_B0 => RxOutputData(0),
    RxOutputData_B1 => RxOutputData(1),
    RxOutputData_B2 => RxOutputData(2),
    RxOutputData_B3 => RxOutputData(3),
    RxOutputData_B4 => RxOutputData(4),
    RxOutputData_B5 => RxOutputData(5),
    RxOutputData_B6 => RxOutputData(6),
    RxOutputData_B7 => RxOutputData(7),
    RxDataWrite_n   => RxDataWrite_n,   -- Receive Data Valid
    RxStatusWrite_n => RxStatusWrite_n, -- Receive Status Valid
    RxEnable        => '1'
  );
--=====================================================================

RX_FIFO_WR <= not (RxDataWrite_n and RxStatusWrite_n);
RX_FIFO_RDEN <= Rx_FIFO_rclk;
RX_FIFO_rclk <= not Rx_fifo_RDn;

--===================== Rx FIFO Memory ================================  

RX_FIFO : RX_FIFO 
    port map(
	Data => RxoutputData,
	WrClock => Rxclk,
	RdClock => CPU_clk,
	WrEn => Rx_FIFO_WR,
	RdEn => RX_FIFO_RDEN,
	Reset => RX_MEM_RST,
	Q => Tx_CPU_Data,
	Full => RX_FIFO_FF,
	AlmostFull => RX_FIFO_AFF,
	Empty => RX_FIFO_EF,
	AlmostEmpty => RX_FIFO_AEF);
--======================================================================



-- =====================  RX_cnt_Data select ====================================
	process(RST, over_256)     
	  begin
	  	if(RST = '0')then
	  		Rx_cnt_data <= Frame_cnt;
	  	elsif rxclk'event and rxclk = '0' then
			if (over_256 = '1') then
				Rx_cnt_data <= "11111111";
			else
				Rx_cnt_data <= Frame_cnt;
			end if;
		end if;
	  end process;
--==========================================================================



Rx_cnt_fifo_wren <= (not Int_end_frame) or over_256;
rx_cnt_fifo_rden_n <= not rx_cnt_fifo_rden;

--===================== Rx Byte count FIFO Memory ================================  

RX_cnt_FIFO : RX_cnt_FIFO 
    port map(
	Data => Rx_cnt_data,
	WrClock => Rxclk,
	RdClock => CPU_clk,
	WrEn => Rx_cnt_fifo_wren,
	RdEn => rx_cnt_fifo_rden_n,
	Reset => RX_cnt_MEM_RST,
	Q => Rx_SR2,
	Full => RX_cnt_FIFO_FF,
	AlmostFull => RX_cnt_FIFO_AFF,
	Empty => RX_cnt_FIFO_EF,
	AlmostEmpty => RX_cnt_FIFO_AEF);
--======================================================================

--====================== Rx Conrol & Status ============================


process(RST, CPU_CS, CPU_WRn, CPU_ADD, CPU_CLK)
begin
	
	if (rst = '0') then 
		CPU_DATA_OUT <= "11111111";
		Rx_fifo_RDn <= '1';
		rx_cnt_fifo_rden <= '1';
	else
        	if (CPU_CS = '0' and CPU_WRn = '1')then  
        		case CPU_Add is	
				when "000" =>   CPU_DATA_OUT <= Tx_Byte_CNT;            -- Tx byte count
					Rx_fifo_RDn <= '1';  -- Rx fifo Read enable generate
					rx_cnt_fifo_rden <= '1';

				when "010" =>   CPU_DATA_OUT(7) <= sig_end_frame;
					CPU_DATA_OUT(6) <= '0';
					CPU_DATA_OUT(5 downto 3) <= "000";
					CPU_DATA_OUT(2) <= Abort_DET;
					CPU_DATA_OUT(1) <= Octet_ERR;
					CPU_DATA_OUT(0) <= CRC_ERR;
					Rx_fifo_RDn <= '1';
					rx_cnt_fifo_rden <= '1';	
					
				when "011" =>   CPU_DATA_OUT(7 downto 5) <= "000";   -- Tx & Rx FIFO memory available state
					CPU_DATA_OUT(4) <= TX_FIFO_valid;
					CPU_DATA_OUT(3 downto 2) <= "00";
					CPU_DATA_OUT(1) <= RX_CNT_FIFO_valid;
					CPU_DATA_OUT(0) <= RX_FIFO_valid;
					Rx_fifo_RDn <= '1';
					rx_cnt_fifo_rden <= '1';
					
				when "100" =>   CPU_DATA_OUT <= RX_SR2;    -- Rx rest byte count register
					Rx_fifo_RDn <= '1';
					rx_cnt_fifo_rden <= CPU_DSn;
				when "101" =>   CPU_DATA_OUT <= TX_CPU_DATA;    -- CPU Rx FIFO Data Read
					Rx_fifo_RDn <= CPU_DSn;
					rx_cnt_fifo_rden <= '1';
							
				when "110" =>   CPU_DATA_OUT(7 downto 4) <= "1111";
						CPU_DATA_OUT(3) <= Rx_sel;
						CPU_DATA_OUT(2) <= Tx_Fifo_RST;
						CPU_DATA_OUT(1) <= Rx_CNT_Fifo_RST;
						CPU_DATA_OUT(0) <= Rx_Fifo_RST;
					Rx_fifo_RDn <= '1';
					rx_cnt_fifo_rden <= '1';
				when "111" =>   CPU_DATA_OUT <= WR_RD_test;    -- Write and Read test