syv.twr

针对串行存储器M25P80应用的verilog程序

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Release 7.1i Trace H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

C:/Xilinx/bin/nt/trce.exe -ise e:\whao_dyz_cpld\syv\syv.ise -intstyle ise -e 3
-l 3 -s 6 -xml syv syv.ncd -o syv.twr syv.pcf


Design file:              syv.ncd
Physical constraint file: syv.pcf
Device,speed:             xc2s50,-6 (PRODUCTION 1.27 2005-01-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock global_clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
div_clock   |    9.347(R)|global_clk_BUFGP  |   0.000|
led2        |    9.244(R)|global_clk_BUFGP  |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock global_clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
global_clk     |    8.005|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Sun May 25 12:39:28 2008
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Peak Memory Usage: 67 MB