syv.syr

针对串行存储器M25P80应用的verilog程序

 4-bit comparator less             : 1
 5-bit comparator greatequal       : 1
 5-bit comparator less             : 1
 6-bit comparator greatequal       : 1
 6-bit comparator less             : 1
 9-bit comparator greatequal       : 1
 9-bit comparator less             : 1
# Multiplexers                     : 1
 1-bit 8-to-1 multiplexer          : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1988 - Unit <syv>: instances <Mcompar__n0065>, <Mcompar__n0001> of unit <LPM_COMPARE_10> and unit <LPM_COMPARE_5> are dual, second instance is removed
WARNING:Xst:1988 - Unit <syv>: instances <Mcompar__n0064>, <Mcompar__n0002> of unit <LPM_COMPARE_9> and unit <LPM_COMPARE_4> are dual, second instance is removed
WARNING:Xst:1988 - Unit <syv>: instances <Mcompar__n0004>, <Mcompar__n0063> of unit <LPM_COMPARE_2> and unit <LPM_COMPARE_8> are dual, second instance is removed
WARNING:Xst:1988 - Unit <syv>: instances <Mcompar__n0003>, <Mcompar__n0062> of unit <LPM_COMPARE_3> and unit <LPM_COMPARE_7> are dual, second instance is removed

Optimizing unit <syv> ...
Loading device for application Rf_Device from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block syv, actual ratio is 13.
FlipFlop div_clock_t has been replicated 1 time(s)
FlipFlop sys_reset has been replicated 2 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : syv.ngr
Top Level Output File Name         : syv
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 17

Macro Statistics :
# Registers                        : 15
#      1-bit register              : 7
#      24-bit register             : 7
#      8-bit register              : 1
# Multiplexers                     : 1
#      1-bit 8-to-1 multiplexer    : 1
# Adders/Subtractors               : 8
#      24-bit adder                : 7
#      8-bit adder                 : 1
# Comparators                      : 10
#      15-bit comparator less      : 1
#      24-bit comparator lessequal : 1
#      4-bit comparator greatequal : 1
#      4-bit comparator less       : 1
#      5-bit comparator greatequal : 1
#      5-bit comparator less       : 1
#      6-bit comparator greatequal : 1
#      6-bit comparator less       : 1
#      9-bit comparator greatequal : 1
#      9-bit comparator less       : 1

Cell Usage :
# BELS                             : 314
#      GND                         : 1
#      INV                         : 13
#      LUT1                        : 62
#      LUT1_L                      : 10
#      LUT2                        : 18
#      LUT2_L                      : 6
#      LUT3                        : 6
#      LUT3_D                      : 1
#      LUT3_L                      : 8
#      LUT4                        : 16
#      LUT4_D                      : 4
#      LUT4_L                      : 18
#      MUXCY                       : 77
#      MUXF5                       : 2
#      MUXF6                       : 1
#      VCC                         : 1
#      XORCY                       : 70
# FlipFlops/Latches                : 145
#      FDE                         : 66
#      FDR                         : 62
#      FDRE                        : 1
#      FDRS                        : 12
#      FDRSE                       : 1
#      FDS                         : 3
# Clock Buffers                    : 2
#      BUFG                        : 1
#      BUFGP                       : 1
# IO Buffers                       : 15
#      IBUF                        : 8
#      OBUF                        : 7
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                     121  out of    768    15%  
 Number of Slice Flip Flops:           145  out of   1536     9%  
 Number of 4 input LUTs:               149  out of   1536     9%  
 Number of bonded IOBs:                 17  out of     96    17%  
 Number of GCLKs:                        2  out of      4    50%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
div_clock_t:Q                      | BUFG                   | 104   |
global_clk                         | BUFGP                  | 41    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 8.397ns (Maximum Frequency: 119.090MHz)
   Minimum input arrival time before clock: 4.129ns
   Maximum output required time after clock: 6.959ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'div_clock_t:Q'
  Clock period: 7.463ns (frequency: 133.994MHz)
  Total number of paths / destination ports: 547 / 156
-------------------------------------------------------------------------
Delay:               7.463ns (Levels of Logic = 4)
  Source:            j_0 (FF)
  Destination:       datam25_in (FF)
  Source Clock:      div_clock_t:Q rising
  Destination Clock: div_clock_t:Q rising

  Data Path: j_0 to datam25_in
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              8   1.085   1.845  j_0 (j_0)
     LUT3_L:I0->LO         1   0.549   0.000  j<0>3 (MUX_BLOCK_N5)
     MUXF5:I0->O           1   0.315   0.000  j<1>_rn_0 (MUX_BLOCK_j<1>_MUXF51)
     MUXF6:I0->O           1   0.316   1.035  Mmux__COND_1__COND_1 (_COND_1)
     LUT4:I2->O            1   0.549   1.035  _n0052176 (CHOICE186)
     FDRS:S                    0.734          datam25_in
    ----------------------------------------
    Total                      7.463ns (3.548ns logic, 3.915ns route)
                                       (47.5% logic, 52.5% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'global_clk'
  Clock period: 8.397ns (frequency: 119.090MHz)
  Total number of paths / destination ports: 729 / 80
-------------------------------------------------------------------------
Delay:               8.397ns (Levels of Logic = 3)
  Source:            counter_6M_0 (FF)
  Destination:       led2 (FF)
  Source Clock:      global_clk rising
  Destination Clock: global_clk rising

  Data Path: counter_6M_0 to led2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   1.085   1.206  counter_6M_0 (counter_6M_0)
     LUT4:I0->O            1   0.549   1.035  Ker38 (CHOICE122)
     LUT4_D:I0->O          2   0.549   1.206  Ker333 (N3)
     LUT2:I0->O            3   0.549   1.332  _n00781 (_n0078)
     FDE:CE                    0.886          led2
    ----------------------------------------
    Total                      8.397ns (3.618ns logic, 4.779ns route)
                                       (43.1% logic, 56.9% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'div_clock_t:Q'
  Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Offset:              4.129ns (Levels of Logic = 2)
  Source:            data_in<7> (PAD)
  Destination:       data_temp_7 (FF)
  Destination Clock: div_clock_t:Q rising

  Data Path: data_in<7> to data_temp_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.776   1.035  data_in_7_IBUF (data_in_7_IBUF)
     LUT2:I1->O            1   0.549   1.035  _n0055<7>0 (CHOICE84)
     FDRS:S                    0.734          data_temp_7
    ----------------------------------------
    Total                      4.129ns (2.059ns logic, 2.070ns route)
                                       (49.9% logic, 50.1% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'div_clock_t:Q'
  Total number of paths / destination ports: 3 / 3
-------------------------------------------------------------------------
Offset:              6.959ns (Levels of Logic = 1)
  Source:            led1 (FF)
  Destination:       led1 (PAD)
  Source Clock:      div_clock_t:Q rising

  Data Path: led1 to led1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDS:C->Q              2   1.085   1.206  led1 (led1_OBUF)
     OBUF:I->O                 4.668          led1_OBUF (led1)
    ----------------------------------------
    Total                      6.959ns (5.753ns logic, 1.206ns route)
                                       (82.7% logic, 17.3% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'global_clk'
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset:              6.959ns (Levels of Logic = 1)
  Source:            led2 (FF)
  Destination:       led2 (PAD)
  Source Clock:      global_clk rising

  Data Path: led2 to led2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   1.085   1.206  led2 (led2_OBUF)
     OBUF:I->O                 4.668          led2_OBUF (led2)
    ----------------------------------------
    Total                      6.959ns (5.753ns logic, 1.206ns route)
                                       (82.7% logic, 17.3% route)

=========================================================================
CPU : 7.67 / 8.13 s | Elapsed : 7.00 / 8.00 s
 
--> 

Total memory usage is 86896 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    5 (   0 filtered)
Number of infos    :    1 (   0 filtered)