syv.syr

针对串行存储器M25P80应用的verilog程序

Release 7.1i - xst H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: syv.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "syv.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "syv"
Output Format                      : NGC
Target Device                      : xc2s50-6-tq144

---- Source Options
Top Module Name                    : syv
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : syv.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "syv.v"
Module <syv> compiled
No errors in compilation
Analysis of file <"syv.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <syv>.
Module <syv> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================
INFO:Xst:1304 - Contents of register <w_addr24> in unit <syv> never changes during circuit operation. The register is replaced by logic.

Synthesizing Unit <syv>.
    Related source file is "syv.v".
WARNING:Xst:647 - Input <datam25_out> is never used.
    Found finite state machine <FSM_0> for signal <st_wr>.
    -----------------------------------------------------------------------
    | States             | 54                                             |
    | Transitions        | 59                                             |
    | Inputs             | 5                                              |
    | Outputs            | 37                                             |
    | Clock              | div_clock_t (rising_edge)                      |
    | Reset              | sys_reset (positive)                           |
    | Reset type         | synchronous                                    |
    | Reset State        | 000000                                         |
    | Power Up State     | 000000                                         |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <led1>.
    Found 1-bit register for signal <led2>.
    Found 1-bit register for signal <div_clock>.
    Found 1-bit register for signal <datam25_in>.
    Found 1-bit register for signal <s_m25>.
    Found 1-bit 8-to-1 multiplexer for signal <$COND_1>.
    Found 6-bit comparator less for signal <$n0001> created at line 386.
    Found 9-bit comparator less for signal <$n0002> created at line 371.
    Found 4-bit comparator less for signal <$n0003> created at line 361.
    Found 5-bit comparator less for signal <$n0004> created at line 350.
    Found 15-bit comparator less for signal <$n0005> created at line 264.
    Found 24-bit comparator lessequal for signal <$n0043> created at line 73.
    Found 8-bit adder for signal <$n0060> created at line 373.
    Found 4-bit comparator greatequal for signal <$n0062> created at line 361.
    Found 5-bit comparator greatequal for signal <$n0063> created at line 350.
    Found 9-bit comparator greatequal for signal <$n0064> created at line 371.
    Found 6-bit comparator greatequal for signal <$n0065> created at line 386.
    Found 15-bit up counter for signal <count1>.
    Found 6-bit up counter for signal <count2>.
    Found 10-bit up counter for signal <counter_6M>.
    Found 8-bit register for signal <data_temp>.
    Found 1-bit register for signal <div_clock_t>.
    Found 5-bit up counter for signal <i>.
    Found 4-bit up counter for signal <j>.
    Found 9-bit up counter for signal <k>.
    Found 24-bit up counter for signal <resetcount>.
    Found 1-bit register for signal <sys_reset>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   7 Counter(s).
	inferred  15 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred  10 Comparator(s).
	inferred   1 Multiplexer(s).
Unit <syv> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <st_wr[1:54]> with speed1 encoding.
------------------------------------------------------------------
 State  | Encoding
------------------------------------------------------------------
 000000 | 100000000000000000000000000000000000000000000000000000
 000001 | 000000000000000000000000000000000000000000000000000100
 000010 | 000000000000000000000000000000000000000000000000010000
 000011 | 000000000000000000000000000000000000000000000001000000
 000100 | 000000000000000000000000000000000000000000000100000000
 000101 | 000000000000000000000000000000000000000000000000000001
 000110 | 000000000000000000000000000000000000000000000000000010
 000111 | 000000000000000000000000000000000000000000000000001000
 001000 | 000000000000000000000000000000000000000000000000100000
 001001 | 000000000000000000000000000000000000000000000010000000
 001010 | 000000000000000000000000000000000000000000010000000000
 001011 | 000000000000000000000000000000000000000001000000000000
 001100 | 000000000000000000000000000000000000000100000000000000
 001101 | 000000000000000000000000000000000000010000000000000000
 001110 | 000000000000000000000000000000000001000000000000000000
 001111 | 000000000000000000000000000000000000000000001000000000
 010000 | 000000000000000000000000000000000000000000100000000000
 010001 | 000000000000000000000000000000000000000010000000000000
 010010 | 000000000000000000000000000000000000001000000000000000
 010011 | 000000000000000000000000000000000000100000000000000000
 010100 | 000000000000000000000000000000000100000000000000000000
 010101 | 000000000000000000000000000000001000000000000000000000
 010110 | 000000000000000000000001000000000000000000000000000000
 010111 | 000000000000000000000000000001000000000000000000000000
 011000 | 000000000000000000000000000100000000000000000000000000
 011001 | 000000000000000000000000010000000000000000000000000000
 011010 | 000000000000000000000000000000000010000000000000000000
 011011 | 000000000000000000000000000000010000000000000000000000
 011100 | 000000000000000000000000000000100000000000000000000000
 011101 | 000000000000000000000000000010000000000000000000000000
 011110 | 000000000000000000000000001000000000000000000000000000
 011111 | 000000000000000000000100000000000000000000000000000000
 100000 | 000000000000000000010000000000000000000000000000000000
 100001 | 000000000000000001000000000000000000000000000000000000
 100010 | 000000000000000100000000000000000000000000000000000000
 100011 | 000000000000000000000000100000000000000000000000000000
 100100 | 000000000000000000000010000000000000000000000000000000
 100101 | 000000000000000000001000000000000000000000000000000000
 100110 | 000000000000000000100000000000000000000000000000000000
 100111 | 000000000000000010000000000000000000000000000000000000
 101000 | 000000000000001000000000000000000000000000000000000000
 101001 | 000000000000010000000000000000000000000000000000000000
 101010 | 000000000000100000000000000000000000000000000000000000
 101011 | 000000000001000000000000000000000000000000000000000000
 101100 | 000000000010000000000000000000000000000000000000000000
 101101 | 000000000100000000000000000000000000000000000000000000
 101110 | 000000001000000000000000000000000000000000000000000000
 101111 | 000000010000000000000000000000000000000000000000000000
 110000 | 000000100000000000000000000000000000000000000000000000
 110001 | 000010000000000000000000000000000000000000000000000000
 110010 | 000001000000000000000000000000000000000000000000000000
 110011 | 000100000000000000000000000000000000000000000000000000
 110100 | 001000000000000000000000000000000000000000000000000000
 110101 | 010000000000000000000000000000000000000000000000000000
------------------------------------------------------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# Adders/Subtractors               : 1
 8-bit adder                       : 1
# Counters                         : 7
 10-bit up counter                 : 1
 15-bit up counter                 : 1
 24-bit up counter                 : 1
 4-bit up counter                  : 1
 5-bit up counter                  : 1
 6-bit up counter                  : 1
 9-bit up counter                  : 1
# Registers                        : 62
 1-bit register                    : 61
 8-bit register                    : 1
# Comparators                      : 10
 15-bit comparator less            : 1
 24-bit comparator lessequal       : 1
 4-bit comparator greatequal       : 1