scaler_p.vhd

VHDL描述的简易图像缩小模块

library ieee;
use ieee.std_logic_1164.all;

package scaler_p is
	type s_state is (EA,
 	                 EB);
	component rom_m is
		PORT
			(
				address		: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
				clock		: IN STD_LOGIC ;
				q		: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
			);
	END component;
	
	component rom_n is
		PORT
			(
				address		: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
				clock		: IN STD_LOGIC ;
				q		: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
			);
	END component;
	
	component dram is
		PORT
	(
		data_a		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		wren_a		: IN STD_LOGIC  := '1';
		address_a		: IN STD_LOGIC_VECTOR (17 DOWNTO 0);
		data_b		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		address_b		: IN STD_LOGIC_VECTOR (17 DOWNTO 0);
		wren_b		: IN STD_LOGIC  := '1';
		clock		: IN STD_LOGIC ;
		q_a		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		q_b		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
	END component;
	
	component scaler_core is
		port(clk    : in std_logic;
		 reset  : in std_logic;  --复位
		 gray_i : in std_logic_vector(7 downto 0); --输入灰度
		 r_sync_i : in std_logic;  --行同步
		 z_sync_i : in std_logic;  --帧同步
		 gray_o : out std_logic_vector(7 downto 0); --输出灰度
		 r_sync_o : out std_logic;
		 z_sync_o : out std_logic;
		 
		 rom_adr_m : out std_logic_vector(8 downto 0);
		 rom_data_m : in std_logic_vector(9 downto 0);
		
		 rom_adr_n : out std_logic_vector(8 downto 0);
		 rom_data_n : in std_logic_vector(9 downto 0);
		 
		 dram_adr_r : out std_logic_vector(17 downto 0);
		 dram_adr_w : out std_logic_vector(17 downto 0);
		 dram_wren : out std_logic;
		 dram_data : out std_logic_vector(7 downto 0);
		 dram_q : in std_logic_vector(7 downto 0));
	end component;
end package;