scaler.vhd

VHDL描述的简易图像缩小模块

library ieee;
use ieee.std_logic_1164.all;
use work.scaler_p.all;

entity scaler is
	port(
			clk : in std_logic;
			reset : in std_logic;
			r_sync_i : in std_logic;
			z_sync_i : in std_logic;
			gray_i : in std_logic_vector(7 downto 0);
			
			r_sync_o : out std_logic;
			z_sync_o : out std_logic;
			gray_o : out std_logic_vector(7 downto 0));
end scaler;

architecture rtl of scaler is
	signal s_rom_adr_m : std_logic_vector(8 downto 0);
	signal s_rom_adr_n : std_logic_vector(8 downto 0);
	signal s_rom_data_m : std_logic_vector(9 downto 0);
	signal s_rom_data_n : std_logic_vector(9 downto 0);
	signal s_dram_adr_r : std_logic_vector(17 downto 0);
	signal s_dram_adr_w : std_logic_vector(17 downto 0);
	signal s_dram_wren : std_logic;
	signal s_dram_data : std_logic_vector(7 downto 0);
	signal s_dram_q : std_logic_vector(7 downto 0);
	

begin

u1 : scaler_core
	port map( 	clk => clk,
				reset => reset,
				gray_i => gray_i,
				r_sync_i => r_sync_i,
				z_sync_i => z_sync_i,
				gray_o => gray_o,
				r_sync_o => r_sync_o,
				z_sync_o => z_sync_o,
				
				rom_adr_m => s_rom_adr_m,
				rom_data_m => s_rom_data_m,
				
				rom_adr_n => s_rom_adr_n,
				rom_data_n => s_rom_data_n,
				
				dram_adr_r => s_dram_adr_r,
		 		dram_adr_w => s_dram_adr_w,
		 		dram_wren => s_dram_wren,
		 		dram_data => s_dram_data,
		 		dram_q => s_dram_q
		);
	
u2 : dram
	port map(	data_a => s_dram_data,	
				wren_a => s_dram_wren,		
				address_a => s_dram_adr_w,
				address_b => s_dram_adr_r,
				wren_b => '0',
				data_b => (others => '0'),
--				q_a =>  
				clock => clk,
				q_b => s_dram_q
			);

u3 : rom_m
	port map(	address	=> s_rom_adr_m,
				clock => clk,
				q => s_rom_data_m
			);

u4 : rom_n
	port map(	address	=> s_rom_adr_n,
				clock => clk,
				q => s_rom_data_n
			);

end rtl;