scaler_core.vhd

VHDL描述的简易图像缩小模块

library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.scaler_p.all;

entity scaler_core is
	port(clk    : in std_logic;
		 reset  : in std_logic;  --复位
		 gray_i : in std_logic_vector(7 downto 0); --输入灰度
		 r_sync_i : in std_logic;  --行同步
		 z_sync_i : in std_logic;  --帧同步
		 gray_o : out std_logic_vector(7 downto 0); --输出灰度
		 r_sync_o : out std_logic;
		 z_sync_o : out std_logic;
		 
		 rom_adr_m : out std_logic_vector(8 downto 0);
		 rom_data_m : in std_logic_vector(9 downto 0);
		
		 rom_adr_n : out std_logic_vector(8 downto 0);
		 rom_data_n : in std_logic_vector(9 downto 0);
		 
		 dram_adr_r : out std_logic_vector(17 downto 0);
		 dram_adr_w : out std_logic_vector(17 downto 0);
		 dram_wren : out std_logic;
		 dram_data : out std_logic_vector(7 downto 0);
		 dram_q : in std_logic_vector(7 downto 0));
end entity;

architecture rtl of scaler_core is

	signal clk2 : std_logic;
	signal state : s_state;
	signal in_m : std_logic_vector(9 downto 0);
	signal in_n : std_logic_vector(9 downto 0);
	signal s_gray_i : std_logic_vector(7 downto 0);
	signal s_gray_o : std_logic_vector(7 downto 0);
	--signal new_m : std_logic_vector(9 downto 0);
	--signal new_n : std_logic_vector(9 downto 0);
	signal m : std_logic_vector(8 downto 0);
	signal n : std_logic_vector(8 downto 0);
	signal s_rom_adr_m : std_logic_vector(8 downto 0);
	signal s_rom_adr_n : std_logic_vector(8 downto 0);
	signal s_read_en : std_logic;
	
	signal r_m : std_logic_vector(9 downto 0);
	signal r_n : std_logic_vector(9 downto 0);
	signal bak_r_m : std_logic_vector(9 downto 0);
	signal bak_r_n : std_logic_vector(9 downto 0);
	
--	signal s_equ : std_logic;
	signal bak_m : std_logic_vector(8 downto 0);
	signal bak_n : std_logic_vector(8 downto 0);
	
	
begin
	
	gray_o <= s_gray_o;
	rom_adr_m <= s_rom_adr_m;
	rom_adr_n <= s_rom_adr_n;
	dram_adr_w <= bak_m & bak_n;
	dram_adr_r <= bak_r_m(8 downto 0) & bak_r_n(8 downto 0);
	r_sync_o <= r_sync_i;
	z_sync_o <= z_sync_i;
	s_rom_adr_m <= m;
   s_rom_adr_n <= n;
	
	process (clk,reset)
	begin
		if reset = '1' then
			clk2 <= '0';
		else
			if clk = '1' and clk'event then
				clk2 <= not clk2;
			end if;
		end if;
	end process;
	
	process(clk,reset)
	begin
		
		if reset='1' then
			state <= EA;
			m <= (others => '0');
			n <= (others => '0');
			in_m <= (others => '0');
			in_n <= (others => '0');
			s_read_en <= '0';
--			new_m <= (others => '0');
--			new_n <= (others => '0');

		else
			if clk='1' and clk'event then
				dram_wren <= '0';
	--			s_read_en <= '0';
				if r_sync_i = '0' and z_sync_i = '0' then
				case state is
	--				when STARTUP =>
	--					if r_sync_i = '1' then
	--						state <= EA;
	--					end if;
					when EA =>


		--				s_gray_i <= gray_i;
						state <= EB;
					when EB =>
						if in_m = rom_data_m and in_n = rom_data_n then
							bak_m <= m;
							bak_n <= n;
							dram_data <= gray_i;
							dram_wren <= '1';
							if n = 511 then
								n <= (others => '0');
								if m = 409 then
									m <= (others => '0');
								else
									m <= m + 1;
								end if;
							else
								n <= n + 1;
							end if;						
						end if;
						s_read_en <= '1';
						if in_n = 719 then
							in_n <= (others => '0');
							if in_m = 575 then
								in_m <= (others => '0');
							else
								in_m <= in_m + 1;
							end if;
						else
							in_n <= in_n + 1;
						end if;
			--			new_m <= rom_data_m;
			--			new_n <= rom_data_n;
					   state <= EA;
					when others =>
						NULL;
				end case;
				else
				   s_read_en <= '0';
				end if;
			end if;
		end if;
	end process;
	
	process(clk2,reset)
		
	begin
		if reset='1' then
			r_n <= (others => '0');
			r_m <= (others => '0');
		else
			if clk2='1' and clk2'event and s_read_en = '1' then

				if r_n < 512 and r_m <410 then
					bak_r_m <= r_m;
					bak_r_n <= r_n;
					s_gray_o <= dram_q;
				else
					s_gray_o <= (others => '0');
				end if;
				if r_n = 719 then
					r_n <= (others => '0');
					if r_m = 575 then
						r_m <= (others => '0');
					else
						r_m <= r_m + 1;
					end if;
				else
					r_n <= r_n + 1;
				end if;
			end if;
		end if;
	end process;

end rtl;