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📄 lcd_v.tan.rpt

📁 FPGA实现的LCD接口
💻 RPT
📖 第 1 页 / 共 5 页
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; N/A                                     ; 106.56 MHz ( period = 9.384 ns )                    ; lcd:inst1|address[1]                                                                                                                                                                                                     ; lcd:inst1|address[3]                                                                                                                                                                                                     ; mclk       ; mclk     ; None                        ; None                      ; 8.078 ns                ;
; N/A                                     ; 112.17 MHz ( period = 8.915 ns )                    ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_h5a:auto_generated|safe_q[0]                                        ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_np92:auto_generated|altsyncram_tg91:altsyncram1|ram_block2a0~portb_we_reg                                                      ; mclk       ; mclk     ; None                        ; None                      ; 8.714 ns                ;
; N/A                                     ; 112.45 MHz ( period = 8.893 ns )                    ; lcd:inst1|address[3]                                                                                                                                                                                                     ; lcd:inst1|data[0]~reg0                                                                                                                                                                                                   ; mclk       ; mclk     ; None                        ; None                      ; 7.587 ns                ;
; N/A                                     ; 112.45 MHz ( period = 8.893 ns )                    ; lcd:inst1|address[3]                                                                                                                                                                                                     ; lcd:inst1|data[1]~reg0                                                                                                                                                                                                   ; mclk       ; mclk     ; None                        ; None                      ; 7.587 ns                ;
; N/A                                     ; 112.45 MHz ( period = 8.893 ns )                    ; lcd:inst1|address[3]                                                                                                                                                                                                     ; lcd:inst1|data[2]~reg0                                                                                                                                                                                                   ; mclk       ; mclk     ; None                        ; None                      ; 7.587 ns                ;
; N/A                                     ; 112.45 MHz ( period = 8.893 ns )                    ; lcd:inst1|address[3]                                                                                                                                                                                                     ; lcd:inst1|data[3]~reg0                                                                                                                                                                                                   ; mclk       ; mclk     ; None                        ; None                      ; 7.587 ns                ;
; N/A                                     ; 112.45 MHz ( period = 8.893 ns )                    ; lcd:inst1|address[3]                                                                                                                                                                                                     ; lcd:inst1|data[4]~reg0                                                                                                                                                                                                   ; mclk       ; mclk     ; None                        ; None                      ; 7.587 ns                ;
; N/A                                     ; 112.45 MHz ( period = 8.893 ns )                    ; lcd:inst1|address[3]                                                                                                                                                                                                     ; lcd:inst1|data[5]~reg0                                                                                                                                                                                                   ; mclk       ; mclk     ; None                        ; None                      ; 7.587 ns                ;
; N/A                                     ; 112.45 MHz ( period = 8.893 ns )                    ; lcd:inst1|address[3]                                                                                                                                                                                                     ; lcd:inst1|data[6]~reg0                                                                                                                                                                                                   ; mclk       ; mclk     ; None                        ; None                      ; 7.587 ns                ;
; N/A                                     ; 112.45 MHz ( period = 8.893 ns )                    ; lcd:inst1|address[3]                                                                                                                                                                                                     ; lcd:inst1|always4~0                                                                                                                                                                                                      ; mclk       ; mclk     ; None                        ; None                      ; 7.587 ns                ;
; N/A                                     ; 112.63 MHz ( period = 8.879 ns )                    ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_1a9:auto_generated|safe_q[10] ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_1a9:auto_generated|safe_q[4]  ; mclk       ; mclk     ; None                        ; None                      ; 8.609 ns                ;
; N/A                                     ; 112.63 MHz ( period = 8.879 ns )                    ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_1a9:auto_generated|safe_q[10] ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_1a9:auto_generated|safe_q[1]  ; mclk       ; mclk     ; None                        ; None                      ; 8.609 ns                ;
; N/A                                     ; 112.63 MHz ( period = 8.879 ns )                    ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_1a9:auto_generated|safe_q[10] ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_1a9:auto_generated|safe_q[3]  ; mclk       ; mclk     ; None                        ; None                      ; 8.609 ns                ;
; N/A                                     ; 112.63 MHz ( period = 8.879 ns )                    ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_1a9:auto_generated|safe_q[10] ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_1a9:auto_generated|safe_q[9]  ; mclk       ; mclk     ; None                        ; None                      ; 8.609 ns                ;
; N/A                                     ; 112.63 MHz ( period = 8.879 ns )                    ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_1a9:auto_generated|safe_q[10] ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_1a9:auto_generated|safe_q[6]  ; mclk       ; mclk     ; None                        ; None                      ; 8.609 ns                ;
; N/A                                     ; 112.63 MHz ( period = 8.879 ns )                    ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_1a9:auto_generated|safe_q[10] ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_1a9:auto_generated|safe_q[10] ; mclk       ; mclk     ; None                        ; None                      ; 8.609 ns                ;
; N/A                                     ; 112.63 MHz ( period = 8.879 ns )                    ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_1a9:auto_generated|safe_q[10] ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_1a9:auto_generated|safe_q[0]  ; mclk       ; mclk     ; None                        ; None                      ; 8.609 ns                ;
; N/A                                     ; 112.63 MHz ( period = 8.879 ns )                    ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_1a9:auto_generated|safe_q[10] ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_1a9:auto_generated|safe_q[2]  ; mclk       ; mclk     ; None                        ; None                      ; 8.609 ns                ;
; N/A                                     ; 112.63 MHz ( period = 8.879 ns )                    ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_1a9:auto_generated|safe_q[10] ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_1a9:auto_generated|safe_q[7]  ; mclk       ; mclk     ; None                        ; None                      ; 8.609 ns                ;
; N/A                                     ; 112.63 MHz ( period = 8.879 ns )                    ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_1a9:auto_generated|safe_q[10] ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_1a9:auto_generated|safe_q[8]  ; mclk       ; mclk     ; None                        ; None                      ; 8.609 ns                ;
; N/A                                     ; 112.63 MHz ( period = 8.879 ns )                    ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_1a9:auto_generated|safe_q[10] ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_1a9:auto_generated|safe_q[5]  ; mclk       ; mclk     ; None                        ; None                      ; 8.609 ns                ;
; N/A                                     ; 112.64 MHz ( period = 8.878 ns )                    ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_h5a:auto_generated|safe_q[0]                                        ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_np92:auto_generated|altsyncram_tg91:altsyncram1|ram_block2a1~portb_we_reg                                                      ; mclk       ; mclk     ; None                        ; None                      ; 8.679 ns                ;
; N/A                                     ; 112.70 MHz ( period = 8.873 ns )                    ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_h5a:auto_generated|safe_q[1]                                        ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_np92:auto_generated|altsyncram_tg91:altsyncram1|ram_block2a0~portb_we_reg                                                      ; mclk       ; mclk     ; None                        ; None                      ; 8.672 ns                ;
; N/A                                     ; 112.88 MHz ( period = 8.859 ns )                    ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_h5a:auto_generated|safe_q[0]                                        ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_np92:auto_generated|altsyncram_tg91:altsyncram1|ram_block2a15~portb_we_reg                                                     ; mclk       ; mclk     ; None                        ; None                      ; 8.662 ns                ;
; N/A                                     ; 113.17 MHz ( period = 8.836 ns )                    ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_h5a:auto_generated|safe_q[1]                                        ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_np92:auto_generated|altsyncram_tg91:altsyncram1|ram_block2a1~portb_we_reg                                                      ; mclk       ; mclk     ; None                        ; None                      ; 8.637 ns                ;
; N/A                                     ; 113.37 MHz ( period = 8.821 ns )                    ; lcd:inst1|address[2]                                                                                                                                                                                                     ; lcd:inst1|state.SHIFT                                                                                                                                                                                                    ; mclk       ; mclk     ; None                        ; None                      ; 7.515 ns                ;
; N/A                                     ; 113.37 MHz ( period = 8.821 ns )                    ; lcd:inst1|address[2]                                                                                                                                                                                                     ; lcd:inst1|state.WRITERAM                                                                                                                                                                                                 ; mclk       ; mclk     ; None                        ; None                      ; 7.515 ns                ;
; N/A                                     ; 113.42 MHz ( period = 8.817 ns )                    ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_h5a:auto_generated|safe_q[1]                                        ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_np92:auto_generated|altsyncram_tg91:altsyncram1|ram_block2a15~portb_we_reg                                                     ; mclk       ; mclk     ; None                        ; None                      ; 8.620 ns                ;
; N/A                                     ; 113.62 MHz ( period = 8.801 ns )                    ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_h5a:auto_generated|safe_q[2]                                        ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_np92:auto_generated|altsyncram_tg91:altsyncram1|ram_block2a0~portb_we_reg                                                      ; mclk       ; mclk     ; None                        ; None                      ; 8.600 ns                ;
; N/A                                     ; 113.88 MHz ( period = 8.781 ns )                    ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_h5a:auto_generated|safe_q[3]                                        ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_np92:auto_generated|altsyncram_tg91:altsyncram1|ram_block2a0~portb_we_reg                                                      ; mclk       ; mclk     ; None                        ; None                      ; 8.580 ns                ;
; N/A                                     ; 114.10 MHz ( period = 8.764 ns )                    ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_h5a:auto_generated|safe_q[2]                                        ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_np92:auto_generated|altsyncram_tg91:altsyncram1|ram_block2a1~portb_we_reg                                                      ; mclk       ; mclk     ; None                        ; None                      ; 8.565 ns                ;
; N/A                                     ; 114.35 MHz ( period = 8.745 ns )                    ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_h5a:auto_generated|safe_q[2]                                        ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_np92:auto_generated|altsyncram_tg91:altsyncram1|ram_block2a15~portb_we_reg                                                     ; mclk       ; mclk     ; None                        ; None                      ; 8.548 ns                ;
; N/A                                     ; 114.36 MHz ( period = 8.744 ns )                    ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_h5a:auto_generated|safe_q[3]                                        ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_np92:auto_generated|altsyncram_tg91:altsyncram1|ram_block2a1~portb_we_reg                                                      ; mclk       ; mclk     ; None                        ; None

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