lcd_v.tan.rpt

FPGA实现的LCD接口

; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                          ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name              ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; mclk                         ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
; altera_internal_jtag~TCKUTAP ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'mclk'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                             ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                                                                                     ; To                                                                                                                                                                                                                       ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 56.58 MHz ( period = 17.674 ns )                    ; lcd:inst1|lcd_e                                                                                                                                                                                                          ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[14]                                                                                                                                                                    ; mclk       ; mclk     ; None                        ; None                      ; 0.892 ns                ;
; N/A                                     ; 73.63 MHz ( period = 13.581 ns )                    ; lcd:inst1|lcd_rs                                                                                                                                                                                                         ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[15]                                                                                                                                                                    ; mclk       ; mclk     ; None                        ; None                      ; 2.622 ns                ;
; N/A                                     ; 74.92 MHz ( period = 13.348 ns )                    ; lcd:inst1|address[2]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[10]                                                                                                                                                                    ; mclk       ; mclk     ; None                        ; None                      ; 2.418 ns                ;
; N/A                                     ; 76.56 MHz ( period = 13.061 ns )                    ; lcd:inst1|address[4]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[12]                                                                                                                                                                    ; mclk       ; mclk     ; None                        ; None                      ; 2.108 ns                ;
; N/A                                     ; 76.75 MHz ( period = 13.029 ns )                    ; lcd:inst1|address[5]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[13]                                                                                                                                                                    ; mclk       ; mclk     ; None                        ; None                      ; 2.076 ns                ;
; N/A                                     ; 76.79 MHz ( period = 13.023 ns )                    ; lcd:inst1|address[3]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[11]                                                                                                                                                                    ; mclk       ; mclk     ; None                        ; None                      ; 2.093 ns                ;
; N/A                                     ; 76.88 MHz ( period = 13.008 ns )                    ; lcd:inst1|address[1]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[9]                                                                                                                                                                     ; mclk       ; mclk     ; None                        ; None                      ; 2.078 ns                ;
; N/A                                     ; 77.24 MHz ( period = 12.946 ns )                    ; lcd:inst1|always4~0                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[6]                                                                                                                                                                     ; mclk       ; mclk     ; None                        ; None                      ; 1.996 ns                ;
; N/A                                     ; 77.25 MHz ( period = 12.945 ns )                    ; lcd:inst1|always4~0                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[3]                                                                                                                                                                     ; mclk       ; mclk     ; None                        ; None                      ; 1.995 ns                ;
; N/A                                     ; 79.23 MHz ( period = 12.622 ns )                    ; lcd:inst1|always4~0                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[0]                                                                                                                                                                     ; mclk       ; mclk     ; None                        ; None                      ; 1.672 ns                ;