lcd_v.tan.rpt

FPGA实现的LCD接口

programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+---------------------------------------------+------------------------------------------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack                                    ; Required Time ; Actual Time                      ; From                                                                                                                                                     ; To                                                    ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+------------------------------------------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A                                      ; None          ; 4.616 ns                         ; rst                                                                                                                                                      ; lcd:inst1|clkcnt[3]                                   ;                              ; mclk                         ; 0            ;
; Worst-case tco                              ; N/A                                      ; None          ; 24.142 ns                        ; lcd:inst1|lcd_rs                                                                                                                                         ; lcd_rs                                                ; mclk                         ;                              ; 0            ;
; Worst-case tpd                              ; N/A                                      ; None          ; 2.901 ns                         ; altera_internal_jtag~TDO                                                                                                                                 ; altera_reserved_tdo                                   ;                              ;                              ; 0            ;
; Worst-case th                               ; N/A                                      ; None          ; 6.819 ns                         ; rst                                                                                                                                                      ; lcd:inst1|lcd_rs                                      ;                              ; mclk                         ; 0            ;
; Clock Setup: 'mclk'                         ; N/A                                      ; None          ; 56.58 MHz ( period = 17.674 ns ) ; lcd:inst1|lcd_e                                                                                                                                          ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[14] ; mclk                         ; mclk                         ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A                                      ; None          ; 95.20 MHz ( period = 10.504 ns ) ; sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out|dffs[0] ; sld_hub:sld_hub_inst|hub_tdo                          ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Hold: 'mclk'                          ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; lcd:inst1|state.WRITERAM                                                                                                                                 ; lcd:inst1|state.WRITERAM                              ; mclk                         ; mclk                         ; 12           ;
; Total number of failed paths                ;                                          ;               ;                                  ;                                                                                                                                                          ;                                                       ;                              ;                              ; 12           ;
+---------------------------------------------+------------------------------------------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------+------------------------------+------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C35F484C8       ;      ;    ;             ;
; Timing Models                                         ; Preliminary        ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;