lcd_v.hif

FPGA实现的LCD接口

OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
aclr
clock
data0
data10
data11
data12
data13
data14
data15
data16
data17
data18
data19
data1
data20
data21
data22
data2
data3
data4
data5
data6
data7
data8
data9
enable
load
shiftin
shiftout
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|lpm_constant.inc
1107574524
c:|altera|quartus50|libraries|megafunctions|dffeea.inc
1107574164
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1131033050
}
# end
# entity
sld_rom_sr
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|sld_rom_sr.vhd
1131032874
4
# storage
db|lcd_v.(45).cnf
db|lcd_v.(45).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
common_ip_version
0
PARAMETER_DEC
USR
n_bits
32
PARAMETER_DEC
USR
word_size
4
PARAMETER_DEC
USR
}
# end
# entity
sld_hub
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|sld_hub.vhd
1131032874
4
# storage
db|lcd_v.(46).cnf
db|lcd_v.(46).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
sld_hub_ip_version
1
PARAMETER_UNKNOWN
USR
sld_hub_ip_minor_version
2
PARAMETER_UNKNOWN
USR
sld_common_ip_version
0
PARAMETER_UNKNOWN
USR
device_family
Cyclone II
PARAMETER_UNKNOWN
USR
n_nodes
1
PARAMETER_UNKNOWN
USR
n_sel_bits
1
PARAMETER_UNKNOWN
USR
n_node_ir_bits
7
PARAMETER_UNKNOWN
USR
node_info
00011000000000000110111000000000
PARAMETER_BIN
USR
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|sld_hub.vhd
1131032874
}
# end
# entity
sld_jtag_state_machine
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|sld_hub.vhd
1131032874
4
# storage
db|lcd_v.(47).cnf
db|lcd_v.(47).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
ip_major_version
1
PARAMETER_DEC
USR
ip_minor_version
2
PARAMETER_DEC
USR
common_ip_version
0
PARAMETER_DEC
USR
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|sld_hub.vhd
1131032874
}
# end
# entity
lpm_shiftreg
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|lpm_shiftreg.tdf
1114012454
6
# storage
db|lcd_v.(48).cnf
db|lcd_v.(48).cnf
# user_parameter {
LPM_WIDTH
10
PARAMETER_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
aclr
clock
enable
q0
q1
q2
q3
q4
q5
q6
q7
q8
q9
shiftin
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|lpm_constant.inc
1107574524
c:|altera|quartus50|libraries|megafunctions|dffeea.inc
1107574164
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1131033050
}
# end
# entity
lpm_decode
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|lpm_decode.tdf
1114012450
6
# storage
db|lcd_v.(49).cnf
db|lcd_v.(49).cnf
# user_parameter {
LPM_WIDTH
3
PARAMETER_DEC
USR
LPM_DECODES
8
PARAMETER_DEC
USR
LPM_PIPELINE
1
PARAMETER_DEC
USR
CASCADE_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
decode_rpe
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
aclr
clken
clock
data0
data1
data2
enable
eq0
eq1
eq2
eq3
eq7
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|lpm_constant.inc
1107574524
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1131033050
c:|altera|quartus50|libraries|megafunctions|lpm_compare.inc
1107574500
c:|altera|quartus50|libraries|megafunctions|altshift.inc
1107573438
c:|altera|quartus50|libraries|megafunctions|declut.inc
1107574136
}
# end
# entity
sld_dffex
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|sld_dffex.vhd
1131032874
4
# storage
db|lcd_v.(51).cnf
db|lcd_v.(51).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
size
1
PARAMETER_DEC
USR
}
# end
# entity
sld_dffex
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|sld_dffex.vhd
1131032874
4
# storage
db|lcd_v.(52).cnf
db|lcd_v.(52).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
size
8
PARAMETER_DEC
USR
}
# end
# entity
sld_dffex
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|sld_dffex.vhd
1131032874
4
# storage
db|lcd_v.(53).cnf
db|lcd_v.(53).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
size
7
PARAMETER_DEC
USR
}
# end
# entity
sld_rom_sr
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|sld_rom_sr.vhd
1131032874
4
# storage
db|lcd_v.(54).cnf
db|lcd_v.(54).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
common_ip_version
0
PARAMETER_DEC
USR
n_bits
64
PARAMETER_DEC
USR
word_size
4
PARAMETER_DEC
USR
}
# end
# entity
lcd_v
# case_insensitive
# source_file
lcd_v.bdf
1125124642
23
# storage
db|lcd_v.(0).cnf
db|lcd_v.(0).cnf
# hierarchies {
|
}
# end
# entity
lcd
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
lcd.v
1134779398
7
# storage
db|lcd_v.(1).cnf
db|lcd_v.(1).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
IDLE
00000000000
PARAMETER_BIN
USR
CLEAR
00000000001
PARAMETER_BIN
USR
RETURNCURSOR
00000000010
PARAMETER_BIN
USR
SETMODE
00000000100
PARAMETER_BIN
USR
SWITCHMODE
00000001000
PARAMETER_BIN
USR
SHIFT
00000010000
PARAMETER_BIN
USR
SETFUNCTION
00000100000
PARAMETER_BIN
USR
SETCGRAM
00001000000
PARAMETER_BIN
USR
SETDDRAM
00010000000
PARAMETER_BIN
USR
READFLAG
00100000000
PARAMETER_BIN
USR
WRITERAM
01000000000
PARAMETER_BIN
USR
READRAM
10000000000
PARAMETER_BIN
USR
cur_inc
1
PARAMETER_UNKNOWN
USR
cur_dec
0
PARAMETER_UNKNOWN
USR
cur_shift
1
PARAMETER_UNKNOWN
USR
cur_noshift
0
PARAMETER_UNKNOWN
USR
open_display
1
PARAMETER_UNKNOWN
USR
open_cur
0
PARAMETER_UNKNOWN
USR
blank_cur
0
PARAMETER_UNKNOWN
USR
shift_display
1
PARAMETER_UNKNOWN
USR
shift_cur
0
PARAMETER_UNKNOWN
USR
right_shift
1
PARAMETER_UNKNOWN
USR
left_shift
0
PARAMETER_UNKNOWN
USR
datawidth8
1
PARAMETER_UNKNOWN
USR
datawidth4
0
PARAMETER_UNKNOWN
USR
twoline
1
PARAMETER_UNKNOWN
USR
oneline
0
PARAMETER_UNKNOWN
USR
font5x10
1
PARAMETER_UNKNOWN
USR
font5x7
0
PARAMETER_UNKNOWN
USR
}
# hierarchies {
lcd:inst1
}
# end
# entity
cntr_909
# case_insensitive
# source_file
db|cntr_909.tdf
1165301302
6
# storage
db|lcd_v.(16).cnf
db|lcd_v.(16).cnf
# used_port {
clock
clk_en
aset
q0
q1
q2
q3
q4
q5
q6
q7
q8
q9
q10
}
# end
# entity
cntr_1a9
# case_insensitive
# source_file
db|cntr_1a9.tdf
1165301302
6
# storage
db|lcd_v.(19).cnf
db|lcd_v.(19).cnf
# used_port {
clock
clk_en
cnt_en
aclr
sclr
q0
q1
q2
q3
q4
q5
q6
q7
q8
q9
q10
}
# end
# entity
cntr_h5a
# case_insensitive
# source_file
db|cntr_h5a.tdf
1165301304
6
# storage
db|lcd_v.(33).cnf
db|lcd_v.(33).cnf
# used_port {
clock
clk_en
aclr
q0
q1
q2
q3
q4
q5
q6
q7
q8
q9
q10
cout
}
# end
# entity
altsyncram_np92
# case_insensitive
# source_file
db|altsyncram_np92.tdf
1165301306
6
# storage
db|lcd_v.(36).cnf
db|lcd_v.(36).cnf
# used_port {
wren_a
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
data_a8
data_a9
data_a10
data_a11
data_a12
data_a13
data_a14
data_a15
data_a16
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
address_a10
address_b0
address_b1
address_b2
address_b3
address_b4
address_b5
address_b6
address_b7
address_b8
address_b9
address_b10
clock0
clock1
clocken1
q_b0
q_b1
q_b2
q_b3
q_b4
q_b5
q_b6
q_b7
q_b8
q_b9
q_b10
q_b11
q_b12
q_b13
q_b14
q_b15
q_b16
}
# end
# entity
altsyncram_tg91
# case_insensitive
# source_file
db|altsyncram_tg91.tdf
1165301306
6
# storage
db|lcd_v.(37).cnf
db|lcd_v.(37).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
address_a10
address_b0
address_b1
address_b2
address_b3
address_b4
address_b5
address_b6
address_b7
address_b8
address_b9
address_b10
clock0
clock1
clocken0
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
data_a8
data_a9
data_a10
data_a11
data_a12
data_a13
data_a14
data_a15
data_a16
data_b0
data_b1
data_b2
data_b3
data_b4
data_b5
data_b6
data_b7
data_b8
data_b9
data_b10
data_b11
data_b12
data_b13
data_b14
data_b15
data_b16
wren_a
wren_b
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_a8
q_a9
q_a10
q_a11
q_a12
q_a13
q_a14
q_a15
q_a16
}
# memory_file {
none
0
}
# end
# entity
cntr_178
# case_insensitive
# source_file
db|cntr_178.tdf
1165301306
6
# storage
db|lcd_v.(40).cnf
db|lcd_v.(40).cnf
# used_port {
clock
clk_en
aclr
q0
q1
q2
q3
q4
}
# end
# entity
cntr_7v7
# case_insensitive
# source_file
db|cntr_7v7.tdf
1165301306
6
# storage
db|lcd_v.(42).cnf
db|lcd_v.(42).cnf
# used_port {
clock
clk_en
aclr
q0
q1
q2
q3
q4
q5
q6
q7
q8
q9
q10
}
# end
# entity
decode_rpe
# case_insensitive
# source_file
db|decode_rpe.tdf
1165301308
6
# storage
db|lcd_v.(50).cnf
db|lcd_v.(50).cnf
# used_port {
aclr
clken
clock
data0
data1
data2
enable
eq0
eq1
eq2
eq3
eq4
eq5
eq6
eq7
}
# end
# complete