lcd_v.fit.qmsg

FPGA实现的LCD接口

{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 4 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 4%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Warning" "WDAT_PRELIMINARY_TIMING" "EP2C35F484C8 " "Warning: Timing characteristics of device EP2C35F484C8 are preliminary" {  } {  } 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "11 " "Warning: Found 11 output pins without output pin load capacitance assignment" { { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "lcd_e 0 " "Warning: Pin \"lcd_e\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "lcd_rw 0 " "Warning: Pin \"lcd_rw\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "lcd_rs 0 " "Warning: Pin \"lcd_rs\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "data\[7\] 0 " "Warning: Pin \"data\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "data\[6\] 0 " "Warning: Pin \"data\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "data\[5\] 0 " "Warning: Pin \"data\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "data\[4\] 0 " "Warning: Pin \"data\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "data\[3\] 0 " "Warning: Pin \"data\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "data\[2\] 0 " "Warning: Pin \"data\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "data\[1\] 0 " "Warning: Pin \"data\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "data\[0\] 0 " "Warning: Pin \"data\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0}  } {  } 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "11 " "Warning: Found 11 output pins without output pin load capacitance assignment" { { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "lcd_e 0 " "Warning: Pin \"lcd_e\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "lcd_rw 0 " "Warning: Pin \"lcd_rw\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "lcd_rs 0 " "Warning: Pin \"lcd_rs\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "data\[7\] 0 " "Warning: Pin \"data\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "data\[6\] 0 " "Warning: Pin \"data\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "data\[5\] 0 " "Warning: Pin \"data\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "data\[4\] 0 " "Warning: Pin \"data\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "data\[3\] 0 " "Warning: Pin \"data\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "data\[2\] 0 " "Warning: Pin \"data\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "data\[1\] 0 " "Warning: Pin \"data\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "data\[0\] 0 " "Warning: Pin \"data\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0}  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_signaltap:auto_signaltap_0\|reset_all~clkctrl " "Info: Node sld_signaltap:auto_signaltap_0\|reset_all~clkctrl uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:auto_signaltap_0\|bypass_reg_out " "Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0\|bypass_reg_out -- routed using non-global resources" {  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "" { sld_signaltap:auto_signaltap_0|bypass_reg_out } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|bypass_reg_out" } } } } { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 420 -1 0 } } { "E:/code/EP2C35/S6_LCD_V/proj/lcd_v.fld" "" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/lcd_v.fld" "" "" { sld_signaltap:auto_signaltap_0|bypass_reg_out } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[1\] " "Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[1\] -- routed using non-global resources" {  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "" { sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[1\]" } } } } { "lpm_shiftreg.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_shiftreg.tdf" 54 7 0 } } { "E:/code/EP2C35/S6_LCD_V/proj/lcd_v.fld" "" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/lcd_v.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[0\] " "Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[0\] -- routed using non-global resources" {  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "" { sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[0\]" } } } } { "lpm_shiftreg.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_shiftreg.tdf" 54 7 0 } } { "E:/code/EP2C35/S6_LCD_V/proj/lcd_v.fld" "" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/lcd_v.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[3\] " "Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[3\] -- routed using non-global resources" {  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "" { sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[3\]" } } } } { "lpm_shiftreg.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_shiftreg.tdf" 54 7 0 } } { "E:/code/EP2C35/S6_LCD_V/proj/lcd_v.fld" "" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/lcd_v.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[2\] " "Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[2\] -- routed using non-global resources" {  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "" { sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offl