lcd_v.fit.qmsg

FPGA实现的LCD接口

{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "0.900 ns register register " "Info: Estimated most critical path is register to register delay of 0.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd:inst1\|lcd_e 1 REG LAB_X40_Y19 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X40_Y19; Fanout = 3; REG Node = 'lcd:inst1\|lcd_e'" {  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "" { lcd:inst1|lcd_e } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.790 ns) + CELL(0.110 ns) 0.900 ns sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[14\] 2 REG LAB_X40_Y19 5 " "Info: 2: + IC(0.790 ns) + CELL(0.110 ns) = 0.900 ns; Loc. = LAB_X40_Y19; Fanout = 5; REG Node = 'sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[14\]'" {  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "0.900 ns" { lcd:inst1|lcd_e sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[14] } "NODE_NAME" } "" } } { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 437 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.110 ns 12.22 % " "Info: Total cell delay = 0.110 ns ( 12.22 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.790 ns 87.78 % " "Info: Total interconnect delay = 0.790 ns ( 87.78 % )" {  } {  } 0}  } { { "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP2C35/S6_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP2C35/S6_LCD_V/proj/" "" "0.900 ns" { lcd:inst1|lcd_e sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[14] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}