lcd_v.map.qmsg

FPGA实现的LCD接口

{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(129) " "Warning: Verilog HDL assignment warning at lcd.v(129): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 129 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(131) " "Warning: Verilog HDL assignment warning at lcd.v(131): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 131 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(133) " "Warning: Verilog HDL assignment warning at lcd.v(133): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 133 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(135) " "Warning: Verilog HDL assignment warning at lcd.v(135): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 135 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(137) " "Warning: Verilog HDL assignment warning at lcd.v(137): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 137 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(138) " "Warning: Verilog HDL assignment warning at lcd.v(138): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 138 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(142) " "Warning: Verilog HDL assignment warning at lcd.v(142): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 142 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(143) " "Warning: Verilog HDL assignment warning at lcd.v(143): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 143 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "lcd.v(57) " "Warning: (10270) Verilog HDL statement warning at lcd.v(57): incomplete Case Statement has no default case item" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 57 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_FUNCTION_MAY_RETURN_X" "ddram lcd.v(54) " "Warning: Verilog HDL Function Declaration warning at lcd.v(54): function \"ddram\" may return a don't care value because its output register may not be assigned a value in every possible path through function" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 54 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 lcd.v(145) " "Warning: Verilog HDL assignment warning at lcd.v(145): truncated value with size 32 to match size of target (6)" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 145 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(150) " "Warning: Verilog HDL assignment warning at lcd.v(150): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 150 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(151) " "Warning: Verilog HDL assignment warning at lcd.v(151): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 151 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_NET" "ddram\[7\] 0 lcd.v(54) " "Warning: Tied undriven net \"ddram\[7\]\" at lcd.v(54) to 0" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 54 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_NET" "ddram\[6\] 0 lcd.v(54) " "Warning: Tied undriven net \"ddram\[6\]\" at lcd.v(54) to 0" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 54 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_NET" "ddram\[5\] 0 lcd.v(54) " "Warning: Tied undriven net \"ddram\[5\]\" at lcd.v(54) to 0" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 54 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_NET" "ddram\[4\] 0 lcd.v(54) " "Warning: Tied undriven net \"ddram\[4\]\" at lcd.v(54) to 0" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 54 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_NET" "ddram\[3\] 0 lcd.v(54) " "Warning: Tied undriven net \"ddram\[3\]\" at lcd.v(54) to 0" {  } { { "lcd.v" "" { Text "E:/code/EP2C35/S6_LCD_V/proj/lcd.v" 54 0 0 } }  } 0}