ram.v

来自「16位的RISC_CPU」· Verilog 代码 · 共 20 行

// --------------- RAM和ROM ----------------------------------------
module ram( data, addr, ena, read, write );
inout [15:0] data;
input [9:0] addr;
input ena;
input read, write;
reg [15:0] ram [10'h3ff:0];

assign data = ( !read && ena )?  ram[addr] : 16'bzzzzzzzzzzzzzzzz;

always @(posedge write)
begin
	if (ena)
        ram[addr]<=data;
end
endmodule