freq_cnt.tan.qmsg

利用FPGA实现的脉宽测试技术,基于VHDL,测试误差为时钟周期

{ "Info" "ITDB_FULL_TCO_RESULT" "clk freq\[8\] freq\[8\]~reg0 8.127 ns register " "Info: tco from clock \"clk\" to destination pin \"freq\[8\]\" through register \"freq\[8\]~reg0\" is 8.127 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.865 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.865 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "freq_cnt.vhd" "" { Text "E:/tool_stud/freq_cnt/freq_cnt.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 56 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 56; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "freq_cnt.vhd" "" { Text "E:/tool_stud/freq_cnt/freq_cnt.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.920 ns) + CELL(0.666 ns) 2.865 ns freq\[8\]~reg0 3 REG LCFF_X33_Y14_N29 1 " "Info: 3: + IC(0.920 ns) + CELL(0.666 ns) = 2.865 ns; Loc. = LCFF_X33_Y14_N29; Fanout = 1; REG Node = 'freq\[8\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.586 ns" { clk~clkctrl freq[8]~reg0 } "NODE_NAME" } } { "freq_cnt.vhd" "" { Text "E:/tool_stud/freq_cnt/freq_cnt.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.04 % ) " "Info: Total cell delay = 1.806 ns ( 63.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.059 ns ( 36.96 % ) " "Info: Total interconnect delay = 1.059 ns ( 36.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.865 ns" { clk clk~clkctrl freq[8]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.865 ns" { clk clk~combout clk~clkctrl freq[8]~reg0 } { 0.000ns 0.000ns 0.139ns 0.920ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "freq_cnt.vhd" "" { Text "E:/tool_stud/freq_cnt/freq_cnt.vhd" 57 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.958 ns + Longest register pin " "Info: + Longest register to pin delay is 4.958 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns freq\[8\]~reg0 1 REG LCFF_X33_Y14_N29 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X33_Y14_N29; Fanout = 1; REG Node = 'freq\[8\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { freq[8]~reg0 } "NODE_NAME" } } { "freq_cnt.vhd" "" { Text "E:/tool_stud/freq_cnt/freq_cnt.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.672 ns) + CELL(3.286 ns) 4.958 ns freq\[8\] 2 PIN PIN_163 0 " "Info: 2: + IC(1.672 ns) + CELL(3.286 ns) = 4.958 ns; Loc. = PIN_163; Fanout = 0; PIN Node = 'freq\[8\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.958 ns" { freq[8]~reg0 freq[8] } "NODE_NAME" } } { "freq_cnt.vhd" "" { Text "E:/tool_stud/freq_cnt/freq_cnt.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.286 ns ( 66.28 % ) " "Info: Total cell delay = 3.286 ns ( 66.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.672 ns ( 33.72 % ) " "Info: Total interconnect delay = 1.672 ns ( 33.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.958 ns" { freq[8]~reg0 freq[8] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.958 ns" { freq[8]~reg0 freq[8] } { 0.000ns 1.672ns } { 0.000ns 3.286ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.865 ns" { clk clk~clkctrl freq[8]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.865 ns" { clk clk~combout clk~clkctrl freq[8]~reg0 } { 0.000ns 0.000ns 0.139ns 0.920ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.958 ns" { freq[8]~reg0 freq[8] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.958 ns" { freq[8]~reg0 freq[8] } { 0.000ns 1.672ns } { 0.000ns 3.286ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "freq\[19\]~reg0 reset clk 0.669 ns register " "Info: th for register \"freq\[19\]~reg0\" (data pin = \"reset\", clock pin = \"clk\") is 0.669 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.860 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.860 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "freq_cnt.vhd" "" { Text "E:/tool_stud/freq_cnt/freq_cnt.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 56 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 56; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "freq_cnt.vhd" "" { Text "E:/tool_stud/freq_cnt/freq_cnt.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.915 ns) + CELL(0.666 ns) 2