freq_cnt.vhd

利用FPGA实现的脉宽测试技术,基于VHDL,测试误差为时钟周期

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY freq_cnt IS
	PORT(
			clk : IN std_logic;
			reset : IN std_logic;
			signel : IN std_logic;
			lock : IN std_logic;
			freq : OUT std_logic_vector(26 downto 0)
		);
END freq_cnt;

ARCHITECTURE freq_detect OF freq_cnt IS
SIGNAL count_int:std_logic_vector(26 downto 0); --std_logic_vector(0 to 26);
SIGNAL lock_buf:std_logic;
SIGNAL signel_buf:std_logic;
BEGIN

	PROCESS --(clk,reset)
	BEGIN
		WAIT UNTIL rising_edge(clk);
			lock_buf <= lock; 
	END PROCESS;
	
	PROCESS --(clk,reset)
	BEGIN
		WAIT UNTIL rising_edge(clk);
			signel_buf <= signel; 
	END PROCESS;
	
		
	PROCESS--(clk,reset)
	BEGIN
		WAIT UNTIL rising_edge(clk);
		IF reset = '1' THEN
			count_int <= (OTHERS => '0');
		ELSE
			IF lock_buf = '0' AND lock = '1' THEN --100000000-1
				count_int<= (OTHERS => '0');
			ELSIF signel = '1' AND signel_buf = '0' THEN
				count_int <= count_int + 1;
			END IF;
		END IF;
	END PROCESS;
	
	
	PROCESS--(clk,reset) 
	BEGIN
		WAIT UNTIL rising_edge(clk);
		IF reset = '1' THEN
			freq <= (OTHERS => '0');
		ELSIF lock_buf = '0' AND lock = '1' THEN
			freq <= count_int;
		END IF;
	END PROCESS;	
	
	
END freq_detect;