de2_lcm_ccd.tan.rpt

在altera DE2 的开发板上采集图像

; Enable Recovery/Removal analysis                                    ; Off                ;                 ;                           ;             ;
; Enable Clock Latency                                                ; Off                ;                 ;                           ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;                 ;                           ;             ;
; Number of source nodes to report per destination node               ; 10                 ;                 ;                           ;             ;
; Number of destination nodes to report                               ; 10                 ;                 ;                           ;             ;
; Number of paths to report                                           ; 200                ;                 ;                           ;             ;
; Report Minimum Timing Checks                                        ; Off                ;                 ;                           ;             ;
; Use Fast Timing Models                                              ; Off                ;                 ;                           ;             ;
; Report IO Paths Separately                                          ; Off                ;                 ;                           ;             ;
; Perform Multicorner Analysis                                        ; On                 ;                 ;                           ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;                 ;                           ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;                 ;                           ;             ;
; Cut Timing Path                                                     ; On                 ; delayed_wrptr_g ; rs_dgwp|dffpipe9|dffe10a  ; dcfifo_m2o1 ;
; Cut Timing Path                                                     ; On                 ; rdptr_g         ; ws_dgrp|dffpipe11|dffe12a ; dcfifo_m2o1 ;
+---------------------------------------------------------------------+--------------------+-----------------+---------------------------+-------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                                                            ;
+---------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                                                           ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+---------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ;                    ; PLL output ; 100.0 MHz        ; 0.000 ns      ; 0.000 ns     ; CLOCK_50 ; 2                     ; 1                   ; -2.358 ns ;              ;
; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk1 ;                    ; PLL output ; 100.0 MHz        ; 0.000 ns      ; 0.000 ns     ; CLOCK_50 ; 2                     ; 1                   ; -5.358 ns ;              ;
; CLOCK_50                                                                  ;                    ; User Pin   ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; GPIO_1[10]                                                                ;                    ; User Pin   ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
+---------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                          ; To                                                                                                                                          ; From Clock                                                                ; To Clock                                                                  ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
; 3.323 ns                                ; 149.77 MHz ( period = 6.677 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[3] ; Sdram_Control_4Port:u6|WR_MASK[0]                                                                                                           ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.789 ns                  ; 6.466 ns                ;
; 3.323 ns                                ; 149.77 MHz ( period = 6.677 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[3] ; Sdram_Control_4Port:u6|WR_MASK[1]                                                                                                           ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.789 ns                  ; 6.466 ns                ;
; 3.323 ns                                ; 149.77 MHz ( period = 6.677 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[3] ; Sdram_Control_4Port:u6|mWR                                                                                                                  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.789 ns                  ; 6.466 ns                ;
; 3.347 ns                                ; 150.31 MHz ( period = 6.653 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[0] ; Sdram_Control_4Port:u6|WR_MASK[0]                                                                                                           ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.789 ns                  ; 6.442 ns                ;