de2_lcm_ccd.tan.rpt

来自「在altera DE2 的开发板上采集图像」· RPT 代码 · 共 186 行 · 第 1/5 页

; 3.347 ns                                ; 150.31 MHz ( period = 6.653 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[0] ; Sdram_Control_4Port:u6|WR_MASK[1]                                                                                                           ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.789 ns                  ; 6.442 ns                ;
; 3.347 ns                                ; 150.31 MHz ( period = 6.653 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[0] ; Sdram_Control_4Port:u6|mWR                                                                                                                  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.789 ns                  ; 6.442 ns                ;
; 3.367 ns                                ; 150.76 MHz ( period = 6.633 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[0] ; Sdram_Control_4Port:u6|WR_MASK[0]                                                                                                           ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.789 ns                  ; 6.422 ns                ;
; 3.367 ns                                ; 150.76 MHz ( period = 6.633 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[0] ; Sdram_Control_4Port:u6|WR_MASK[1]                                                                                                           ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.789 ns                  ; 6.422 ns                ;
; 3.367 ns                                ; 150.76 MHz ( period = 6.633 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[0] ; Sdram_Control_4Port:u6|mWR                                                                                                                  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.789 ns                  ; 6.422 ns                ;
; 3.386 ns                                ; 151.19 MHz ( period = 6.614 ns )                    ; Sdram_Control_4Port:u6|IN_REQ                                                                                                 ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9] ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.787 ns                  ; 6.401 ns                ;
; 3.394 ns                                ; 151.38 MHz ( period = 6.606 ns )                    ; Sdram_Control_4Port:u6|WR_MASK[0]                                                                                             ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9] ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.777 ns                  ; 6.383 ns                ;
; 3.398 ns                                ; 151.47 MHz ( period = 6.602 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[3] ; Sdram_Control_4Port:u6|mADDR[10]                                                                                                            ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.788 ns                  ; 6.390 ns                ;
; 3.422 ns                                ; 152.02 MHz ( period = 6.578 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[0] ; Sdram_Control_4Port:u6|mADDR[10]                                                                                                            ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.788 ns                  ; 6.366 ns                ;
; 3.438 ns                                ; 152.39 MHz ( period = 6.562 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[1] ; Sdram_Control_4Port:u6|WR_MASK[0]                                                                                                           ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.789 ns                  ; 6.351 ns                ;
; 3.438 ns                                ; 152.39 MHz ( period = 6.562 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[1] ; Sdram_Control_4Port:u6|WR_MASK[1]                                                                                                           ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.789 ns                  ; 6.351 ns                ;
; 3.438 ns                                ; 152.39 MHz ( period = 6.562 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[1] ; Sdram_Control_4Port:u6|mWR                                                                                                                  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.789 ns                  ; 6.351 ns                ;
; 3.441 ns                                ; 152.46 MHz ( period = 6.559 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[1] ; Sdram_Control_4Port:u6|WR_MASK[0]                                                                                                           ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.789 ns                  ; 6.348 ns                ;
; 3.441 ns                                ; 152.46 MHz ( period = 6.559 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[1] ; Sdram_Control_4Port:u6|WR_MASK[1]                                                                                                           ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.789 ns                  ; 6.348 ns                ;
; 3.441 ns                                ; 152.46 MHz ( period = 6.559 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[1] ; Sdram_Control_4Port:u6|mWR                                                                                                                  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.789 ns                  ; 6.348 ns                ;
; 3.442 ns                                ; 152.49 MHz ( period = 6.558 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[0] ; Sdram_Control_4Port:u6|mADDR[10]                                                                                                            ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.788 ns                  ; 6.346 ns                ;
; 3.453 ns                                ; 152.74 MHz ( period = 6.547 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[3] ; Sdram_Control_4Port:u6|mADDR[19]                                                                                                            ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.796 ns                  ; 6.343 ns                ;
; 3.457 ns                                ; 152.84 MHz ( period = 6.543 ns )                    ; Sdram_Control_4Port:u6|IN_REQ                                                                                                 ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8] ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.787 ns                  ; 6.330 ns                ;
; 3.465 ns                                ; 153.02 MHz ( period = 6.535 ns )                    ; Sdram_Control_4Port:u6|WR_MASK[0]                                                                                             ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[8] ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.777 ns                  ; 6.312 ns                ;
; 3.471 ns                                ; 153.16 MHz ( period = 6.529 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[3] ; Sdram_Control_4Port:u6|mADDR[15]                                                                                                            ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.788 ns                  ; 6.317 ns                ;
; 3.471 ns                                ; 153.16 MHz ( period = 6.529 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[3] ; Sdram_Control_4Port:u6|mADDR[11]                                                                                                            ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.788 ns                  ; 6.317 ns                ;
; 3.471 ns                                ; 153.16 MHz ( period = 6.529 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[3] ; Sdram_Control_4Port:u6|mADDR[9]                                                                                                             ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.788 ns                  ; 6.317 ns                ;
; 3.471 ns                                ; 153.16 MHz ( period = 6.529 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[3] ; Sdram_Control_4Port:u6|mADDR[8]                                                                                                             ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.788 ns                  ; 6.317 ns                ;
; 3.477 ns                                ; 153.30 MHz ( period = 6.523 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[0] ; Sdram_Control_4Port:u6|mADDR[19]                                                                                                            ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.796 ns                  ; 6.319 ns                ;
; 3.490 ns                                ; 153.61 MHz ( period = 6.510 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[2] ; Sdram_Control_4Port:u6|WR_MASK[0]                                                                                                           ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.789 ns                  ; 6.299 ns                ;
; 3.490 ns                                ; 153.61 MHz ( period = 6.510 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[2] ; Sdram_Control_4Port:u6|WR_MASK[1]                                                                                                           ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.789 ns                  ; 6.299 ns                ;
; 3.490 ns                                ; 153.61 MHz ( period = 6.510 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[2] ; Sdram_Control_4Port:u6|mWR                                                                                                                  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.789 ns                  ; 6.299 ns                ;
; 3.495 ns                                ; 153.73 MHz ( period = 6.505 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[0] ; Sdram_Control_4Port:u6|mADDR[15]                                                                                                            ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.788 ns                  ; 6.293 ns                ;
; 3.495 ns                                ; 153.73 MHz ( period = 6.505 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[0] ; Sdram_Control_4Port:u6|mADDR[11]                                                                                                            ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.788 ns                  ; 6.293 ns                ;
; 3.495 ns                                ; 153.73 MHz ( period = 6.505 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[0] ; Sdram_Control_4Port:u6|mADDR[9]                                                                                                             ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.788 ns                  ; 6.293 ns                ;
; 3.495 ns                                ; 153.73 MHz ( period = 6.505 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[0] ; Sdram_Control_4Port:u6|mADDR[8]                                                                                                             ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.788 ns                  ; 6.293 ns                ;
; 3.497 ns                                ; 153.78 MHz ( period = 6.503 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[0] ; Sdram_Control_4Port:u6|mADDR[19]                                                                                                            ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.796 ns                  ; 6.299 ns                ;
; 3.502 ns                                ; 153.89 MHz ( period = 6.498 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[2] ; Sdram_Control_4Port:u6|WR_MASK[0]                                                                                                           ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.789 ns                  ; 6.287 ns                ;
; 3.502 ns                                ; 153.89 MHz ( period = 6.498 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[2] ; Sdram_Control_4Port:u6|WR_MASK[1]                                                                                                           ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.789 ns                  ; 6.287 ns                ;
; 3.502 ns                                ; 153.89 MHz ( period = 6.498 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[2] ; Sdram_Control_4Port:u6|mWR                                                                                                                  ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.789 ns                  ; 6.287 ns                ;
; 3.513 ns                                ; 154.15 MHz ( period = 6.487 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_brp|dffe8a[1] ; Sdram_Control_4Port:u6|mADDR[10]                                                                                                            ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.788 ns                  ; 6.275 ns                ;
; 3.515 ns                                ; 154.20 MHz ( period = 6.485 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[0] ; Sdram_Control_4Port:u6|mADDR[15]                                                                                                            ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.788 ns                  ; 6.273 ns                ;
; 3.515 ns                                ; 154.20 MHz ( period = 6.485 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[0] ; Sdram_Control_4Port:u6|mADDR[11]                                                                                                            ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.788 ns                  ; 6.273 ns                ;