de2_lcm_ccd.tan.rpt

在altera DE2 的开发板上采集图像

programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                             ;
+------------------------------------------------------------------------------------------+----------+-----------------------------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------+
; Type                                                                                     ; Slack    ; Required Time                     ; Actual Time                      ; From                                                                                                                          ; To                                              ; From Clock                                                                ; To Clock                                                                  ; Failed Paths ;
+------------------------------------------------------------------------------------------+----------+-----------------------------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------+
; Worst-case tsu                                                                           ; N/A      ; None                              ; 5.072 ns                         ; KEY[0]                                                                                                                        ; I2C_AV_Config:u9|I2C_Controller:u0|SD[1]        ; --                                                                        ; CLOCK_50                                                                  ; 0            ;
; Worst-case tco                                                                           ; N/A      ; None                              ; 14.280 ns                        ; I2S_LCM_Config:u8|I2S_Controller:u0|mST[4]                                                                                    ; GPIO_0[34]                                      ; CLOCK_50                                                                  ; --                                                                        ; 0            ;
; Worst-case tpd                                                                           ; N/A      ; None                              ; 9.836 ns                         ; SW[14]                                                                                                                        ; LEDR[14]                                        ; --                                                                        ; --                                                                        ; 0            ;
; Worst-case th                                                                            ; N/A      ; None                              ; 3.809 ns                         ; SW[10]                                                                                                                        ; I2C_CCD_Config:u7|mI2C_DATA[2]                  ; --                                                                        ; CLOCK_50                                                                  ; 0            ;
; Clock Setup: 'Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0' ; 3.323 ns ; 100.00 MHz ( period = 10.000 ns ) ; 149.77 MHz ( period = 6.677 ns ) ; Sdram_Control_4Port:u6|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_m2o1:auto_generated|dffpipe_kec:rs_bwp|dffe8a[3] ; Sdram_Control_4Port:u6|WR_MASK[0]               ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'CLOCK_50'                                                                  ; 7.284 ns ; 50.00 MHz ( period = 20.000 ns )  ; 184.09 MHz ( period = 5.432 ns ) ; I2S_LCM_Config:u8|mI2S_STR                                                                                                    ; I2S_LCM_Config:u8|I2S_Controller:u0|mSDATA~en   ; CLOCK_50                                                                  ; CLOCK_50                                                                  ; 0            ;
; Clock Setup: 'GPIO_1[10]'                                                                ; N/A      ; None                              ; 146.13 MHz ( period = 6.843 ns ) ; CCD_Capture:u3|Y_Cont[0]                                                                                                      ; RAW2RGB:u4|mCCD_G[10]                           ; GPIO_1[10]                                                                ; GPIO_1[10]                                                                ; 0            ;
; Clock Hold: 'Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0'  ; 0.391 ns ; 100.00 MHz ( period = 10.000 ns ) ; N/A                              ; Sdram_Control_4Port:u6|command:command1|rw_flag                                                                               ; Sdram_Control_4Port:u6|command:command1|rw_flag ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'CLOCK_50'                                                                   ; 0.391 ns ; 50.00 MHz ( period = 20.000 ns )  ; N/A                              ; I2C_CCD_Config:u7|I2C_Controller:u0|SCLK                                                                                      ; I2C_CCD_Config:u7|I2C_Controller:u0|SCLK        ; CLOCK_50                                                                  ; CLOCK_50                                                                  ; 0            ;
; Total number of failed paths                                                             ;          ;                                   ;                                  ;                                                                                                                               ;                                                 ;                                                                           ;                                                                           ; 0            ;
+------------------------------------------------------------------------------------------+----------+-----------------------------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                                                             ;
+---------------------------------------------------------------------+--------------------+-----------------+---------------------------+-------------+
; Option                                                              ; Setting            ; From            ; To                        ; Entity Name ;
+---------------------------------------------------------------------+--------------------+-----------------+---------------------------+-------------+
; Device Name                                                         ; EP2C35F672C6       ;                 ;                           ;             ;
; Timing Models                                                       ; Final              ;                 ;                           ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;                 ;                           ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;                 ;                           ;             ;
; Cut off read during write signal paths                              ; On                 ;                 ;                           ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;                 ;                           ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;                 ;                           ;             ;
; Ignore Clock Settings                                               ; Off                ;                 ;                           ;             ;
; Analyze latches as synchronous elements                             ; On                 ;                 ;                           ;             ;