de2_lcm_ccd.tan.rpt

来自「在altera DE2 的开发板上采集图像」· RPT 代码 · 共 186 行 · 第 1/5 页

Classic Timing Analyzer report for DE2_LCM_CCD
Tue Jul 01 18:49:31 2008
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0'
  6. Clock Setup: 'CLOCK_50'
  7. Clock Setup: 'GPIO_1[10]'
  8. Clock Hold: 'Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0'
  9. Clock Hold: 'CLOCK_50'
 10. tsu
 11. tco
 12. tpd
 13. th
 14. Timing Analyzer Messages



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; Legal Notice ;
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Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of