_primary.vhd

来自「altera fpga verilog 设计的基于查找表的DCT程序及zigza」· VHDL 代码 · 共 76 行

library verilog;
use verilog.vl_types.all;
entity zigzag is
    port(
        clk             : in     vl_logic;
        ena             : in     vl_logic;
        dstrb           : in     vl_logic;
        din_00          : in     vl_logic_vector(11 downto 0);
        din_01          : in     vl_logic_vector(11 downto 0);
        din_02          : in     vl_logic_vector(11 downto 0);
        din_03          : in     vl_logic_vector(11 downto 0);
        din_04          : in     vl_logic_vector(11 downto 0);
        din_05          : in     vl_logic_vector(11 downto 0);
        din_06          : in     vl_logic_vector(11 downto 0);
        din_07          : in     vl_logic_vector(11 downto 0);
        din_10          : in     vl_logic_vector(11 downto 0);
        din_11          : in     vl_logic_vector(11 downto 0);
        din_12          : in     vl_logic_vector(11 downto 0);
        din_13          : in     vl_logic_vector(11 downto 0);
        din_14          : in     vl_logic_vector(11 downto 0);
        din_15          : in     vl_logic_vector(11 downto 0);
        din_16          : in     vl_logic_vector(11 downto 0);
        din_17          : in     vl_logic_vector(11 downto 0);
        din_20          : in     vl_logic_vector(11 downto 0);
        din_21          : in     vl_logic_vector(11 downto 0);
        din_22          : in     vl_logic_vector(11 downto 0);
        din_23          : in     vl_logic_vector(11 downto 0);
        din_24          : in     vl_logic_vector(11 downto 0);
        din_25          : in     vl_logic_vector(11 downto 0);
        din_26          : in     vl_logic_vector(11 downto 0);
        din_27          : in     vl_logic_vector(11 downto 0);
        din_30          : in     vl_logic_vector(11 downto 0);
        din_31          : in     vl_logic_vector(11 downto 0);
        din_32          : in     vl_logic_vector(11 downto 0);
        din_33          : in     vl_logic_vector(11 downto 0);
        din_34          : in     vl_logic_vector(11 downto 0);
        din_35          : in     vl_logic_vector(11 downto 0);
        din_36          : in     vl_logic_vector(11 downto 0);
        din_37          : in     vl_logic_vector(11 downto 0);
        din_40          : in     vl_logic_vector(11 downto 0);
        din_41          : in     vl_logic_vector(11 downto 0);
        din_42          : in     vl_logic_vector(11 downto 0);
        din_43          : in     vl_logic_vector(11 downto 0);
        din_44          : in     vl_logic_vector(11 downto 0);
        din_45          : in     vl_logic_vector(11 downto 0);
        din_46          : in     vl_logic_vector(11 downto 0);
        din_47          : in     vl_logic_vector(11 downto 0);
        din_50          : in     vl_logic_vector(11 downto 0);
        din_51          : in     vl_logic_vector(11 downto 0);
        din_52          : in     vl_logic_vector(11 downto 0);
        din_53          : in     vl_logic_vector(11 downto 0);
        din_54          : in     vl_logic_vector(11 downto 0);
        din_55          : in     vl_logic_vector(11 downto 0);
        din_56          : in     vl_logic_vector(11 downto 0);
        din_57          : in     vl_logic_vector(11 downto 0);
        din_60          : in     vl_logic_vector(11 downto 0);
        din_61          : in     vl_logic_vector(11 downto 0);
        din_62          : in     vl_logic_vector(11 downto 0);
        din_63          : in     vl_logic_vector(11 downto 0);
        din_64          : in     vl_logic_vector(11 downto 0);
        din_65          : in     vl_logic_vector(11 downto 0);
        din_66          : in     vl_logic_vector(11 downto 0);
        din_67          : in     vl_logic_vector(11 downto 0);
        din_70          : in     vl_logic_vector(11 downto 0);
        din_71          : in     vl_logic_vector(11 downto 0);
        din_72          : in     vl_logic_vector(11 downto 0);
        din_73          : in     vl_logic_vector(11 downto 0);
        din_74          : in     vl_logic_vector(11 downto 0);
        din_75          : in     vl_logic_vector(11 downto 0);
        din_76          : in     vl_logic_vector(11 downto 0);
        din_77          : in     vl_logic_vector(11 downto 0);
        dout            : out    vl_logic_vector(11 downto 0);
        douten          : out    vl_logic
    );
end zigzag;