_primary.vhd

来自「altera fpga verilog 设计的基于查找表的DCT程序及zigza」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity cycloneii_b17mux21 is
    port(
        MO              : out    vl_logic_vector(16 downto 0);
        A               : in     vl_logic_vector(16 downto 0);
        B               : in     vl_logic_vector(16 downto 0);
        S               : in     vl_logic
    );
end cycloneii_b17mux21;