_primary.vhd

来自「altera fpga verilog 设计的基于查找表的DCT程序及zigza」· VHDL 代码 · 共 17 行

library verilog;
use verilog.vl_types.all;
entity dct_mac is
    generic(
        dwidth          : integer := 8;
        cwidth          : integer := 16
    );
    port(
        clk             : in     vl_logic;
        ena             : in     vl_logic;
        dclr            : in     vl_logic;
        din             : in     vl_logic_vector;
        coef            : in     vl_logic_vector;
        result          : out    vl_logic_vector
    );
end dct_mac;