_primary.vhd

来自「altera fpga verilog 设计的基于查找表的DCT程序及zigza」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity dct_syn is
    port(
        clk             : in     vl_logic;
        ena             : in     vl_logic;
        rst             : in     vl_logic;
        dstrb           : in     vl_logic;
        din             : in     vl_logic_vector(7 downto 0);
        dout            : out    vl_logic_vector(11 downto 0);
        den             : out    vl_logic
    );
end dct_syn;