_primary.vhd

来自「altera fpga verilog 设计的基于查找表的DCT程序及zigza」· VHDL 代码 · 共 19 行

library verilog;
use verilog.vl_types.all;
entity fdct is
    generic(
        coef_width      : integer := 11;
        di_width        : integer := 8;
        do_width        : integer := 12
    );
    port(
        clk             : in     vl_logic;
        ena             : in     vl_logic;
        rst             : in     vl_logic;
        dstrb           : in     vl_logic;
        din             : in     vl_logic_vector;
        dout            : out    vl_logic_vector;
        douten          : out    vl_logic
    );
end fdct;