_primary.vhd

来自「altera fpga verilog 设计的基于查找表的DCT程序及zigza」· VHDL 代码 · 共 26 行

library verilog;
use verilog.vl_types.all;
entity dctub is
    generic(
        coef_width      : integer := 16;
        di_width        : integer := 8;
        v               : integer := 0
    );
    port(
        clk             : in     vl_logic;
        ena             : in     vl_logic;
        ddgo            : in     vl_logic;
        x               : in     vl_logic_vector(2 downto 0);
        y               : in     vl_logic_vector(2 downto 0);
        ddin            : in     vl_logic_vector;
        dout0           : out    vl_logic_vector(11 downto 0);
        dout1           : out    vl_logic_vector(11 downto 0);
        dout2           : out    vl_logic_vector(11 downto 0);
        dout3           : out    vl_logic_vector(11 downto 0);
        dout4           : out    vl_logic_vector(11 downto 0);
        dout5           : out    vl_logic_vector(11 downto 0);
        dout6           : out    vl_logic_vector(11 downto 0);
        dout7           : out    vl_logic_vector(11 downto 0)
    );
end dctub;