_primary.vhd

来自「altera fpga verilog 设计的基于查找表的DCT程序及zigza」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity cycloneii_mac_sign_reg is
    port(
        clk             : in     vl_logic;
        d               : in     vl_logic;
        ena             : in     vl_logic;
        aclr            : in     vl_logic;
        q               : out    vl_logic
    );
end cycloneii_mac_sign_reg;