📄 test.map.rpt
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+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |test ; 484 (1) ; 190 ; 0 ; 30 ; 0 ; 294 (1) ; 112 (0) ; 78 (0) ; 128 (0) ; |test ;
; |M10MHz:inst1| ; 77 (77) ; 33 ; 0 ; 0 ; 0 ; 44 (44) ; 30 (30) ; 3 (3) ; 32 (32) ; |test|M10MHz:inst1 ;
; |M10MHz:inst2| ; 77 (77) ; 33 ; 0 ; 0 ; 0 ; 44 (44) ; 30 (30) ; 3 (3) ; 32 (32) ; |test|M10MHz:inst2 ;
; |SetData:inst| ; 329 (329) ; 124 ; 0 ; 0 ; 0 ; 205 (205) ; 52 (52) ; 72 (72) ; 64 (64) ; |test|SetData:inst ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 190 ;
; Number of registers using Synchronous Clear ; 1 ;
; Number of registers using Synchronous Load ; 32 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 87 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------+
; 4:1 ; 32 bits ; 64 LEs ; 32 LEs ; 32 LEs ; Yes ; |test|SetData:inst|count_rom[31] ;
; 8:1 ; 3 bits ; 15 LEs ; 6 LEs ; 9 LEs ; Yes ; |test|SetData:inst|count_end[5] ;
; 8:1 ; 7 bits ; 35 LEs ; 28 LEs ; 7 LEs ; Yes ; |test|SetData:inst|data[31] ;
; 9:1 ; 32 bits ; 192 LEs ; 32 LEs ; 160 LEs ; Yes ; |test|SetData:inst|count[26] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/Documents and Settings/mu/桌面/师兄/test/test.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Wed Apr 09 16:14:10 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off test -c test
Info: Found 1 design units, including 1 entities, in source file test.bdf
Info: Found entity 1: test
Info: Found 2 design units, including 1 entities, in source file SetData.vhd
Info: Found design unit 1: SetData-SetData_body
Info: Found entity 1: SetData
Info: Found 2 design units, including 1 entities, in source file M10MHz.vhd
Info: Found design unit 1: M10MHz-M10MHz_body
Info: Found entity 1: M10MHz
Info: Elaborating entity "test" for the top level hierarchy
Info: Elaborating entity "SetData" for hierarchy "SetData:inst"
Warning: VHDL Signal Declaration warning at SetData.vhd(31): used explicit default value for signal "write_cr_rs1" because signal was never assigned a value
Warning: VHDL Signal Declaration warning at SetData.vhd(32): used explicit default value for signal "read_cr_rs" because signal was never assigned a value
Warning: VHDL Signal Declaration warning at SetData.vhd(33): used explicit default value for signal "write_cr_rs0" because signal was never assigned a value
Warning: VHDL Signal Declaration warning at SetData.vhd(34): used explicit default value for signal "write_csr" because signal was never assigned a value
Warning: VHDL Signal Declaration warning at SetData.vhd(35): used explicit default value for signal "AD" because signal was never assigned a value
Warning: VHDL Signal Declaration warning at SetData.vhd(36): used explicit default value for signal "clearAD" because signal was never assigned a value
Info: Elaborating entity "M10MHz" for hierarchy "M10MHz:inst2"
Info: (10035) Verilog HDL or VHDL information at M10MHz.vhd(17): object "divider" declared but not used
Info: Duplicate registers merged to single register
Info: Duplicate register "SetData:inst|count_end[1]" merged to single register "SetData:inst|count_end[31]"
Info: Duplicate register "SetData:inst|count_end[0]" merged to single register "SetData:inst|count_end[31]"
Info: Duplicate register "SetData:inst|count_end[2]" merged to single register "SetData:inst|count_end[31]"
Info: Duplicate register "SetData:inst|count_end[30]" merged to single register "SetData:inst|count_end[31]"
Info: Duplicate register "SetData:inst|count_end[29]" merged to single register "SetData:inst|count_end[31]"
Info: Duplicate register "SetData:inst|count_end[28]" merged to single register "SetData:inst|count_end[31]"
Info: Duplicate register "SetData:inst|count_end[27]" merged to single register "SetData:inst|count_end[31]"
Info: Duplicate register "SetData:inst|count_end[26]" merged to single register "SetData:inst|count_end[31]"
Info: Duplicate register "SetData:inst|count_end[25]" merged to single register "SetData:inst|count_end[31]"
Info: Duplicate register "SetData:inst|count_end[24]" merged to single register "SetData:inst|count_end[31]"
Info: Duplicate register "SetData:inst|count_end[23]" merged to single register "SetData:inst|count_end[31]"
Info: Duplicate register "SetData:inst|count_end[22]" merged to single register "SetData:inst|count_end[31]"
Info: Duplicate register "SetData:inst|count_end[21]" merged to single register "SetData:inst|count_end[31]"
Info: Duplicate register "SetData:inst|count_end[20]" merged to single register "SetData:inst|count_end[31]"
Info: Duplicate register "SetData:inst|count_end[19]" merged to single register "SetData:inst|count_end[31]"
Info: Duplicate register "SetData:inst|count_end[18]" merged to single register "SetData:inst|count_end[31]"
Info: Duplicate register "SetData:inst|count_end[17]" merged to single register "SetData:inst|count_end[31]"
Info: Duplicate register "SetData:inst|count_end[16]" merged to single register "SetData:inst|count_end[31]"
Info: Duplicate register "SetData:inst|count_end[15]" merged to single register "SetData:inst|count_end[31]"
Info: Duplicate register "SetData:inst|count_end[14]" merged to single register "SetData:inst|count_end[31]"
Info: Duplicate register "SetData:inst|count_end[13]" merged to single register "SetData:inst|count_end[31]"
Info: Duplicate register "SetData:inst|count_end[12]" merged to single register "SetData:inst|count_end[31]"
Info: Duplicate register "SetData:inst|count_end[11]" merged to single register "SetData:inst|count_end[31]"
Info: Duplicate register "SetData:inst|count_end[10]" merged to single register "SetData:inst|count_end[31]"
Info: Duplicate register "SetData:inst|count_end[9]" merged to single register "SetData:inst|count_end[31]"
Info: Duplicate register "SetData:inst|count_end[8]" merged to single register "SetData:inst|count_end[31]"
Info: Duplicate register "SetData:inst|count_end[7]" merged to single register "SetData:inst|count_end[31]"
Info: Duplicate register "SetData:inst|count_end[6]" merged to single register "SetData:inst|count_end[31]"
Info: Duplicate register "SetData:inst|count_end[4]" merged to single register "SetData:inst|count_end[31]"
Info: Duplicate register "SetData:inst|data[29]" merged to single register "SetData:inst|data[30]"
Info: Duplicate register "SetData:inst|data[28]" merged to single register "SetData:inst|data[30]"
Info: Duplicate register "SetData:inst|data[21]" merged to single register "SetData:inst|data[30]"
Info: Duplicate register "SetData:inst|data[20]" merged to single register "SetData:inst|data[30]"
Info: Duplicate register "SetData:inst|data[19]" merged to single register "SetData:inst|data[30]"
Info: Duplicate register "SetData:inst|data[17]" merged to single register "SetData:inst|data[30]"
Info: Duplicate register "SetData:inst|data[16]" merged to single register "SetData:inst|data[30]"
Info: Duplicate register "SetData:inst|data[11]" merged to single register "SetData:inst|data[30]"
Info: Duplicate register "SetData:inst|data[9]" merged to single register "SetData:inst|data[30]"
Info: Duplicate register "SetData:inst|data[8]" merged to single register "SetData:inst|data[30]"
Info: Duplicate register "SetData:inst|data[6]" merged to single register "SetData:inst|data[30]"
Info: Duplicate register "SetData:inst|data[5]" merged to single register "SetData:inst|data[30]"
Info: Duplicate register "SetData:inst|data[4]" merged to single register "SetData:inst|data[30]"
Info: Duplicate register "SetData:inst|data[18]" merged to single register "SetData:inst|data[30]"
Info: Duplicate register "SetData:inst|data[10]" merged to single register "SetData:inst|data[30]"
Info: Duplicate register "SetData:inst|data[23]" merged to single register "SetData:inst|data[26]"
Info: Duplicate register "SetData:inst|data[22]" merged to single register "SetData:inst|data[26]"
Info: Duplicate register "SetData:inst|data[15]" merged to single register "SetData:inst|data[26]"
Info: Duplicate register "SetData:inst|data[13]" merged to single register "SetData:inst|data[26]"
Info: Duplicate register "SetData:inst|data[12]" merged to single register "SetData:inst|data[26]"
Info: Duplicate register "SetData:inst|data[3]" merged to single register "SetData:inst|data[26]"
Info: Duplicate register "SetData:inst|data[2]" merged to single register "SetData:inst|data[26]"
Info: Duplicate register "SetData:inst|data[1]" merged to single register "SetData:inst|data[26]"
Info: Duplicate register "SetData:inst|data[0]" merged to single register "SetData:inst|data[26]"
Info: Duplicate register "SetData:inst|data[14]" merged to single register "SetData:inst|data[26]"
Warning: Reduced register "SetData:inst|count_end[31]" with stuck data_in port to stuck value GND
Warning: Reduced register "SetData:inst|data[30]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
Info: Duplicate register "SetData:inst|count_end[5]" merged to single register "SetData:inst|count_end[3]", power-up level changed
Info: Implemented 514 device resources after synthesis - the final resource count might be different
Info: Implemented 2 input pins
Info: Implemented 28 output pins
Info: Implemented 484 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings
Info: Processing ended: Wed Apr 09 16:14:22 2008
Info: Elapsed time: 00:00:12
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