setdata.vhd

利用Verilog HDL对AD7705进行控制ADC采样

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
---第二层实体：模块1实体------------------------------------
entity SetData is


port
(
	 clk:in std_logic;		
	 SDO_data:in std_logic;				
	 SDI_data:out std_logic;	--Serial data	SDI				
	 Sclkout:out std_logic;	--Serial clock
     SDO_out:out std_logic_vector(23 downto 0);		
	 CS:out std_logic		--latch enable  CS
);
end SetData;

architecture SetData_body of SetData is
-----------------------------------------------------------------------------------------------------------------
signal count:integer:=0;
signal count_end:integer:=0;
signal count_rom:integer:=0;
Signal flag:std_logic:='0';
Signal divider:std_logic:='0';


signal data:std_logic_vector(31 downto 0):="00000000000000000000000000000000" ;
signal SDOdata:std_logic_vector(31 downto 0):="00000000000000000000000000000000" ;

signal write_cr_rs1:std_logic_vector(31 downto 0):="00000011000000000000000010000000";--configuration register--RS=1
signal read_cr_rs:std_logic_vector(31 downto 0):="00001011000000000000000000000000";--configuration register
signal write_cr_rs0:std_logic_vector(31 downto 0):="00000011000000000000000000000000";--configuration register--RS=0
signal write_csr:std_logic_vector(31 downto 0):="00000101110000001111000000001111";
signal AD:std_logic_vector(31 downto 0):="10000000000000000000000000000000";
signal clearAD:std_logic_vector(31 downto 0):="00000000000000000000000000000000";



--------------------------------------------------------------------------





begin
					 

process(clk)
begin

if(clk'event and clk='1')then
   
------------------------------------------
   if count_rom<=9000000 then 
      count_rom<=count_rom+1;
   end if;
------------------------------------软件复位32bits write configuration register RS=1
      if count_rom=2000000 then--clk=2MHz,1s=2000000个时钟周期,
         CS<='0';
         count_end<=32;
      end if;
      if count_rom=2000005 then
         data<=write_cr_rs1;--软件复位32bits
         divider<='0';
         count<=0;
      end if;
      if count_rom=2000072 then
         CS<='1';
      end if;
----------------------------------- read configuration register RS=1
      if count_rom=4000072 then--clk=2MHz,1s=2000000个时钟周期,
         CS<='0';
         count_end<=32;
      end if;
     if count_rom=4000075 then--clk=2MHz,1s=2000000个时钟周期,复位时间
         data<=read_cr_rs;--32bits
         divider<='0';
         count<=0;
      end if;
      if count_rom=4000142 then
         CS<='1';
      end if;
--------------------------------------判断configuration register RS=1
      if (count_rom>4000142 and count_rom<4000145) then
         if SDOdata(7)='0' then 
            count_rom<=1999998;
         else
            null;
         end if;
      end if;
------------------------------------ write configuration register RS=0
      if count_rom=4000145 then
         CS<='0';
         count_end<=32;
      end if;
      if count_rom=4000148 then
         data<=write_cr_rs0;--32bits
         divider<='0';
         count<=0;
      end if;
      if count_rom=4000215 then
         CS<='1';
      end if;
------------------------------------ write configuration register 
      if count_rom=4000445 then
         CS<='0';
         count_end<=32;
      end if;
      if count_rom=4000448 then
         data<=write_cr_rs0;--32bits
         divider<='0';
         count<=0;
      end if;
      if count_rom=4000515 then
         CS<='1';
      end if;
-----------------------------------
------------------------------------ write channel-setup register 
      if count_rom=4000645 then
         CS<='0';
         count_end<=32;
      end if;
      if count_rom=4000648 then
         data<=write_csr;--32bits
         divider<='0';
         count<=0;
      end if;
      if count_rom=4000715 then
         CS<='1';
      end if;
-----------------------------------执行AD转换
      if count_rom=4000915 then
         count_end<=8;
      end if;
      if count_rom=4000918 then
         data<=AD;--8bits
         divider<='0';
         count<=0;
      end if;
-------------------------------------延迟1s>转换时间500ms
      if count_rom>6000937 then
         if SDO_data='1' then --转换出错
            count_rom<=1999998;
             flag<='0';
         else 
            flag<='1';
         end if;
         -------------------------
         if  flag='1' then--发8个脉冲清除SDO标志+24data=32bits
             if count_rom=6000947 then
                count_end<=32;
             end if;
             if  count_rom=6000950 then
                 data<=clearAD;--32bits
                 divider<='0';
                 count<=0;
             end if;
         ---------------------------------       
             if  count_rom>6001100 then
                 SDO_out<=SDOdata(23 downto 0);
             end if;
         end if;
      end if;
      
--------------------------------------------
        -----------------------------------------------------------------------------------
			if divider='0' then
				if count<=count_end then
					count<=count+1;
			    end if;
				if count<=count_end - 1 then		
					SDI_data<=data( count_end - 1 - count);
					SDOdata( count_end - 1 - count)<=SDO_data;
					Sclkout<='0';
					divider<='1';
				else
					Sclkout<='0';
					SDI_data<='0';	
				end if;
			else
				if count<=count_end then
					Sclkout<='1';
					divider<='0';
				end if;
			end if;
		
end if;
end process;
end SetData_body;

		
		
		
		
		
		
		
		
		
		
		
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