test.map.qmsg

利用Verilog HDL对AD7705进行控制ADC采样

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 09 16:14:10 2008 " "Info: Processing started: Wed Apr 09 16:14:10 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off test -c test " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off test -c test" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "test.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file test.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 test " "Info: Found entity 1: test" {  } { { "test.bdf" "" { Schematic "C:/Documents and Settings/mu/桌面/师兄/test/test.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SetData.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file SetData.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 SetData-SetData_body " "Info: Found design unit 1: SetData-SetData_body" {  } { { "SetData.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/SetData.vhd" 19 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 SetData " "Info: Found entity 1: SetData" {  } { { "SetData.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/SetData.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "M10MHz.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file M10MHz.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 M10MHz-M10MHz_body " "Info: Found design unit 1: M10MHz-M10MHz_body" {  } { { "M10MHz.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/M10MHz.vhd" 14 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 M10MHz " "Info: Found entity 1: M10MHz" {  } { { "M10MHz.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/M10MHz.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "test " "Info: Elaborating entity \"test\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SetData SetData:inst " "Info: Elaborating entity \"SetData\" for hierarchy \"SetData:inst\"" {  } { { "test.bdf" "inst" { Schematic "C:/Documents and Settings/mu/桌面/师兄/test/test.bdf" { { 192 496 680 320 "inst" "" } } } }  } 0}
{ "Warning" "WVRFX_VHDL_USED_EXPLICIT_DEFAULT_VALUE" "write_cr_rs1 SetData.vhd(31) " "Warning: VHDL Signal Declaration warning at SetData.vhd(31): used explicit default value for signal \"write_cr_rs1\" because signal was never assigned a value" {  } { { "SetData.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/SetData.vhd" 31 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_USED_EXPLICIT_DEFAULT_VALUE" "read_cr_rs SetData.vhd(32) " "Warning: VHDL Signal Declaration warning at SetData.vhd(32): used explicit default value for signal \"read_cr_rs\" because signal was never assigned a value" {  } { { "SetData.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/SetData.vhd" 32 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_USED_EXPLICIT_DEFAULT_VALUE" "write_cr_rs0 SetData.vhd(33) " "Warning: VHDL Signal Declaration warning at SetData.vhd(33): used explicit default value for signal \"write_cr_rs0\" because signal was never assigned a value" {  } { { "SetData.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/SetData.vhd" 33 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_USED_EXPLICIT_DEFAULT_VALUE" "write_csr SetData.vhd(34) " "Warning: VHDL Signal Declaration warning at SetData.vhd(34): used explicit default value for signal \"write_csr\" because signal was never assigned a value" {  } { { "SetData.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/SetData.vhd" 34 0 0 } }  } 0}