test.tan.qmsg

利用Verilog HDL对AD7705进行控制ADC采样

{ "Info" "ITDB_TH_RESULT" "SetData:inst\|SDOdata\[12\] SDO clk -0.038 ns register " "Info: th for register \"SetData:inst\|SDOdata\[12\]\" (data pin = \"SDO\", clock pin = \"clk\") is -0.038 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.345 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 6.345 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns clk 1 CLK PIN_66 33 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_66; Fanout = 33; CLK Node = 'clk'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "" { clk } "NODE_NAME" } "" } } { "test.bdf" "" { Schematic "C:/Documents and Settings/mu/桌面/师兄/test/test.bdf" { { 104 -240 -72 120 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.494 ns) + CELL(0.827 ns) 2.620 ns M10MHz:inst2\|P10MHz 2 REG LC_X8_Y6_N5 158 " "Info: 2: + IC(0.494 ns) + CELL(0.827 ns) = 2.620 ns; Loc. = LC_X8_Y6_N5; Fanout = 158; REG Node = 'M10MHz:inst2\|P10MHz'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "1.321 ns" { clk M10MHz:inst2|P10MHz } "NODE_NAME" } "" } } { "M10MHz.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/M10MHz.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.096 ns) + CELL(0.629 ns) 6.345 ns SetData:inst\|SDOdata\[12\] 3 REG LC_X22_Y10_N9 1 " "Info: 3: + IC(3.096 ns) + CELL(0.629 ns) = 6.345 ns; Loc. = LC_X22_Y10_N9; Fanout = 1; REG Node = 'SetData:inst\|SDOdata\[12\]'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "3.725 ns" { M10MHz:inst2|P10MHz SetData:inst|SDOdata[12] } "NODE_NAME" } "" } } { "SetData.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/SetData.vhd" 29 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.755 ns 43.42 % " "Info: Total cell delay = 2.755 ns ( 43.42 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.590 ns 56.58 % " "Info: Total interconnect delay = 3.590 ns ( 56.58 % )" {  } {  } 0}  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "6.345 ns" { clk M10MHz:inst2|P10MHz SetData:inst|SDOdata[12] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "6.345 ns" { clk clk~out0 M10MHz:inst2|P10MHz SetData:inst|SDOdata[12] } { 0.000ns 0.000ns 0.494ns 3.096ns } { 0.000ns 1.299ns 0.827ns 0.629ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.013 ns + " "Info: + Micro hold delay of destination is 0.013 ns" {  } { { "SetData.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/SetData.vhd" 29 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.396 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.396 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns SDO 1 PIN PIN_74 26 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_74; Fanout = 26; PIN Node = 'SDO'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "" { SDO } "NODE_NAME" } "" } } { "test.bdf" "" { Schematic "C:/Documents and Settings/mu/桌面/师兄/test/test.bdf" { { 232 144 312 248 "SDO" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.824 ns) + CELL(0.273 ns) 6.396 ns SetData:inst\|SDOdata\[12\] 2 REG LC_X22_Y10_N9 1 " "Info: 2: + IC(4.824 ns) + CELL(0.273 ns) = 6.396 ns; Loc. = LC_X22_Y10_N9; Fanout = 1; REG Node = 'SetData:inst\|SDOdata\[12\]'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "5.097 ns" { SDO SetData:inst|SDOdata[12] } "NODE_NAME" } "" } } { "SetData.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/SetData.vhd" 29 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.572 ns 24.58 % " "Info: Total cell delay = 1.572 ns ( 24.58 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.824 ns 75.42 % " "Info: Total interconnect delay = 4.824 ns ( 75.42 % )" {  } {  } 0}  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "6.396 ns" { SDO SetData:inst|SDOdata[12] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "6.396 ns" { SDO SDO~out0 SetData:inst|SDOdata[12] } { 0.000ns 0.000ns 4.824ns } { 0.000ns 1.299ns 0.273ns } } }  } 0}  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "6.345 ns" { clk M10MHz:inst2|P10MHz SetData:inst|SDOdata[12] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "6.345 ns" { clk clk~out0 M10MHz:inst2|P10MHz SetData:inst|SDOdata[12] } { 0.000ns 0.000ns 0.494ns 3.096ns } { 0.000ns 1.299ns 0.827ns 0.629ns } } } { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "6.396 ns" { SDO SetData:inst|SDOdata[12] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "6.396 ns" { SDO SDO~out0 SetData:inst|SDOdata[12] } { 0.000ns 0.000ns 4.824ns } { 0.000ns 1.299ns 0.273ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 09 16:14:36 2008 " "Info: Processing ended: Wed Apr 09 16:14:36 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}