test.tan.qmsg

利用Verilog HDL对AD7705进行控制ADC采样

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "M10MHz:inst2\|P10MHz " "Info: Detected ripple clock \"M10MHz:inst2\|P10MHz\" as buffer" {  } { { "M10MHz.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/M10MHz.vhd" 9 -1 0 } } { "f:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "M10MHz:inst2\|P10MHz" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register SetData:inst\|count_rom\[13\] register SetData:inst\|count\[28\] 68.68 MHz 14.561 ns Internal " "Info: Clock \"clk\" has Internal fmax of 68.68 MHz between source register \"SetData:inst\|count_rom\[13\]\" and destination register \"SetData:inst\|count\[28\]\" (period= 14.561 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.364 ns + Longest register register " "Info: + Longest register to register delay is 14.364 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SetData:inst\|count_rom\[13\] 1 REG LC_X17_Y5_N7 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y5_N7; Fanout = 7; REG Node = 'SetData:inst\|count_rom\[13\]'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "" { SetData:inst|count_rom[13] } "NODE_NAME" } "" } } { "SetData.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/SetData.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.084 ns) + CELL(0.101 ns) 1.185 ns SetData:inst\|LessThan~4631 2 COMB LC_X18_Y5_N9 4 " "Info: 2: + IC(1.084 ns) + CELL(0.101 ns) = 1.185 ns; Loc. = LC_X18_Y5_N9; Fanout = 4; COMB Node = 'SetData:inst\|LessThan~4631'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "1.185 ns" { SetData:inst|count_rom[13] SetData:inst|LessThan~4631 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.908 ns) + CELL(0.390 ns) 4.483 ns SetData:inst\|CS~460 3 COMB LC_X18_Y5_N8 1 " "Info: 3: + IC(2.908 ns) + CELL(0.390 ns) = 4.483 ns; Loc. = LC_X18_Y5_N8; Fanout = 1; COMB Node = 'SetData:inst\|CS~460'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "3.298 ns" { SetData:inst|LessThan~4631 SetData:inst|CS~460 } "NODE_NAME" } "" } } { "SetData.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/SetData.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.426 ns) + CELL(0.522 ns) 6.431 ns SetData:inst\|CS~461 4 COMB LC_X17_Y7_N9 3 " "Info: 4: + IC(1.426 ns) + CELL(0.522 ns) = 6.431 ns; Loc. = LC_X17_Y7_N9; Fanout = 3; COMB Node = 'SetData:inst\|CS~461'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "1.948 ns" { SetData:inst|CS~460 SetData:inst|CS~461 } "NODE_NAME" } "" } } { "SetData.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/SetData.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.393 ns) + CELL(0.522 ns) 7.346 ns SetData:inst\|CS~462 5 COMB LC_X17_Y7_N7 5 " "Info: 5: + IC(0.393 ns) + CELL(0.522 ns) = 7.346 ns; Loc. = LC_X17_Y7_N7; Fanout = 5; COMB Node = 'SetData:inst\|CS~462'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "0.915 ns" { SetData:inst|CS~461 SetData:inst|CS~462 } "NODE_NAME" } "" } } { "SetData.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/SetData.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.108 ns) + CELL(0.258 ns) 8.712 ns SetData:inst\|reduce_nor~4 6 COMB LC_X17_Y8_N6 2 " "Info: 6: + IC(1.108 ns) + CELL(0.258 ns) = 8.712 ns; Loc. = LC_X17_Y8_N6; Fanout = 2; COMB Node = 'SetData:inst\|reduce_nor~4'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "1.366 ns" { SetData:inst|CS~462 SetData:inst|reduce_nor~4 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.768 ns) + CELL(0.522 ns) 11.002 ns SetData:inst\|data~590 7 COMB LC_X18_Y8_N8 2 " "Info: 7: + IC(1.768 ns) + CELL(0.522 ns) = 11.002 ns; Loc. = LC_X18_Y8_N8; Fanout = 2; COMB Node = 'SetData:inst\|data~590'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "2.290 ns" { SetData:inst|reduce_nor~4 SetData:inst|data~590 } "NODE_NAME" } "" } } { "SetData.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/SetData.vhd" 28 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.365 ns) + CELL(0.390 ns) 11.757 ns SetData:inst\|data\[31\]~591 8 COMB LC_X18_Y8_N9 10 " "Info: 8: + IC(0.365 ns) + CELL(0.390 ns) = 11.757 ns; Loc. = LC_X18_Y8_N9; Fanout = 10; COMB Node = 'SetData:inst\|data\[31\]~591'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "0.755 ns" { SetData:inst|data~590 SetData:inst|data[31]~591 } "NODE_NAME" } "" } } { "SetData.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/SetData.vhd" 28 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.404 ns) + CELL(0.258 ns) 12.419 ns SetData:inst\|count\[26\]~1046 9 COMB LC_X18_Y8_N0 30 " "Info: 9: + IC(0.404 ns) + CELL(0.258 ns) = 12.419 ns; Loc. = LC_X18_Y8_N0; Fanout = 30; COMB Node = 'SetData:inst\|count\[26\]~1046'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "0.662 ns" { SetData:inst|data[31]~591 SetData:inst|count[26]~1046 } "NODE_NAME" } "" } } { "SetData.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/SetData.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.178 ns) + CELL(0.767 ns) 14.364 ns SetData:inst\|count\[28\] 10 REG LC_X18_Y9_N7 4 " "Info: 10: + IC(1.178 ns) + CELL(0.767 ns) = 14.364 ns; Loc. = LC_X18_Y9_N7; Fanout = 4; REG Node = 'SetData:inst\|count\[28\]'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "1.945 ns" { SetData:inst|count[26]~1046 SetData:inst|count[28] } "NODE_NAME" } "" } } { "SetData.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/SetData.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.730 ns 25.97 % " "Info: Total cell delay = 3.730 ns ( 25.97 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.634 ns 74.03 % " "Info: Total interconnect delay = 10.634 ns ( 74.03 % )" {  } {  } 0}  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "14.364 ns" { SetData:inst|count_rom[13] SetData:inst|LessThan~4631 SetData:inst|CS~460 SetData:inst|CS~461 SetData:inst|CS~462 SetData:inst|reduce_nor~4 SetData:inst|data~590 SetData:inst|data[31]~591 SetData:inst|count[26]~1046 SetData:inst|count[28] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "14.364 ns" { SetData:inst|count_rom[13] SetData:inst|LessThan~4631 SetData:inst|CS~460 SetData:inst|CS~461 SetData:inst|CS~462 SetData:inst|reduce_nor~4 SetData:inst|data~590 SetData:inst|data[31]~591 SetData:inst|count[26]~1046 SetData:inst|count[28] } { 0.000ns 1.084ns 2.908ns 1.426ns 0.393ns 1.108ns 1.768ns 0.365ns 0.404ns 1.178ns } { 0.000ns 0.101ns 0.390ns 0.522ns 0.522ns 0.258ns 0.522ns 0.390ns 0.258ns 0.767ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.034 ns - Smallest " "Info: - Smallest clock skew is 0.034 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.345 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 6.345 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns clk 1 CLK PIN_66 33 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_66; Fanout = 33; CLK Node = 'clk'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "" { clk } "NODE_NAME" } "" } } { "test.bdf" "" { Schematic "C:/Documents and Settings/mu/桌面/师兄/test/test.bdf" { { 104 -240 -72 120 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.494 ns) + CELL(0.827 ns) 2.620 ns M10MHz:inst2\|P10MHz 2 REG LC_X8_Y6_N5 158 " "Info: 2: + IC(0.494 ns) + CELL(0.827 ns) = 2.620 ns; Loc. = LC_X8_Y6_N5; Fanout = 158; REG Node = 'M10MHz:inst2\|P10MHz'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "1.321 ns" { clk M10MHz:inst2|P10MHz } "NODE_NAME" } "" } } { "M10MHz.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/M10MHz.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.096 ns) + CELL(0.629 ns) 6.345 ns SetData:inst\|count\[28\] 3 REG LC_X18_Y9_N7 4 " "Info: 3: + IC(3.096 ns) + CELL(0.629 ns) = 6.345 ns; Loc. = LC_X18_Y9_N7; Fanout = 4; REG Node = 'SetData:inst\|count\[28\]'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "3.725 ns" { M10MHz:inst2|P10MHz SetData:inst|count[28] } "NODE_NAME" } "" } } { "SetData.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/SetData.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.755 ns 43.42 % " "Info: Total cell delay = 2.755 ns ( 43.42 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.590 ns 56.58 % " "Info: Total interconnect delay = 3.590 ns ( 56.58 % )" {  } {  } 0}  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "6.345 ns" { clk M10MHz:inst2|P10MHz SetData:inst|count[28] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "6.345 ns" { clk clk~out0 M10MHz:inst2|P10MHz SetData:inst|count[28] } { 0.000ns 0.000ns 0.494ns 3.096ns } { 0.000ns 1.299ns 0.827ns 0.629ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.311 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 6.311 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns clk 1 CLK PIN_66 33 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_66; Fanout = 33; CLK Node = 'clk'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "" { clk } "NODE_NAME" } "" } } { "test.bdf" "" { Schematic "C:/Documents and Settings/mu/桌面/师兄/test/test.bdf" { { 104 -240 -72 120 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.494 ns) + CELL(0.827 ns) 2.620 ns M10MHz:inst2\|P10MHz 2 REG LC_X8_Y6_N5 158 " "Info: 2: + IC(0.494 ns) + CELL(0.827 ns) = 2.620 ns; Loc. = LC_X8_Y6_N5; Fanout = 158; REG Node = 'M10MHz:inst2\|P10MHz'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "1.321 ns" { clk M10MHz:inst2|P10MHz } "NODE_NAME" } "" } } { "M10MHz.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/M10MHz.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.062 ns) + CELL(0.629 ns) 6.311 ns SetData:inst\|count_rom\[13\] 3 REG LC_X17_Y5_N7 7 " "Info: 3: + IC(3.062 ns) + CELL(0.629 ns) = 6.311 ns; Loc. = LC_X17_Y5_N7; Fanout = 7; REG Node = 'SetData:inst\|count_rom\[13\]'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "3.691 ns" { M10MHz:inst2|P10MHz SetData:inst|count_rom[13] } "NODE_NAME" } "" } } { "SetData.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/SetData.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.755 ns 43.65 % " "Info: Total cell delay = 2.755 ns ( 43.65 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.556 ns 56.35 % " "Info: Total interconnect delay = 3.556 ns ( 56.35 % )" {  } {  } 0}  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "6.311 ns" { clk M10MHz:inst2|P10MHz SetData:inst|count_rom[13] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "6.311 ns" { clk clk~out0 M10MHz:inst2|P10MHz SetData:inst|count_rom[13] } { 0.000ns 0.000ns 0.494ns 3.062ns } { 0.000ns 1.299ns 0.827ns 0.629ns } } }  } 0}  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "6.345 ns" { clk M10MHz:inst2|P10MHz SetData:inst|count[28] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "6.345 ns" { clk clk~out0 M10MHz:inst2|P10MHz SetData:inst|count[28] } { 0.000ns 0.000ns 0.494ns 3.096ns } { 0.000ns 1.299ns 0.827ns 0.629ns } } } { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "6.311 ns" { clk M10MHz:inst2|P10MHz SetData:inst|count_rom[13] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "6.311 ns" { clk clk~out0 M10MHz:inst2|P10MHz SetData:inst|count_rom[13] } { 0.000ns 0.000ns 0.494ns 3.062ns } { 0.000ns 1.299ns 0.827ns 0.629ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.198 ns + " "Info: + Micro clock to output delay of source is 0.198 ns" {  } { { "SetData.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/SetData.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.033 ns + " "Info: + Micro setup delay of destination is 0.033 ns" {  } { { "SetData.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/SetData.vhd" 21 -1 0 } }  } 0}  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "14.364 ns" { SetData:inst|count_rom[13] SetData:inst|LessThan~4631 SetData:inst|CS~460 SetData:inst|CS~461 SetData:inst|CS~462 SetData:inst|reduce_nor~4 SetData:inst|data~590 SetData:inst|data[31]~591 SetData:inst|count[26]~1046 SetData:inst|count[28] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "14.364 ns" { SetData:inst|count_rom[13] SetData:inst|LessThan~4631 SetData:inst|CS~460 SetData:inst|CS~461 SetData:inst|CS~462 SetData:inst|reduce_nor~4 SetData:inst|data~590 SetData:inst|data[31]~591 SetData:inst|count[26]~1046 SetData:inst|count[28] } { 0.000ns 1.084ns 2.908ns 1.426ns 0.393ns 1.108ns 1.768ns 0.365ns 0.404ns 1.178ns } { 0.000ns 0.101ns 0.390ns 0.522ns 0.522ns 0.258ns 0.522ns 0.390ns 0.258ns 0.767ns } } } { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "6.345 ns" { clk M10MHz:inst2|P10MHz SetData:inst|count[28] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "6.345 ns" { clk clk~out0 M10MHz:inst2|P10MHz SetData:inst|count[28] } { 0.000ns 0.000ns 0.494ns 3.096ns } { 0.000ns 1.299ns 0.827ns 0.629ns } } } { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "6.311 ns" { clk M10MHz:inst2|P10MHz SetData:inst|count_rom[13] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "6.311 ns" { clk clk~out0 M10MHz:inst2|P10MHz SetData:inst|count_rom[13] } { 0.000ns 0.000ns 0.494ns 3.062ns } { 0.000ns 1.299ns 0.827ns 0.629ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "SetData:inst\|count_rom\[28\] SDO clk 4.115 ns register " "Info: tsu for register \"SetData:inst\|count_rom\[28\]\" (data pin = \"SDO\", clock pin = \"clk\") is 4.115 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.393 ns + Longest pin register " "Info: + Longest pin to register delay is 10.393 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns SDO 1 PIN PIN_74 26 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_74; Fanout = 26; PIN Node = 'SDO'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "" { SDO } "NODE_NAME" } "" } } { "test.bdf" "" { Schematic "C:/Documents and Settings/mu/桌面/师兄/test/test.bdf" { { 232 144 312 248 "SDO" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.214 ns) + CELL(0.390 ns) 7.903 ns SetData:inst\|count_rom\[31\]~5617 2 COMB LC_X17_Y6_N3 32 " "Info: 2: + IC(6.214 ns) + CELL(0.390 ns) = 7.903 ns; Loc. = LC_X17_Y6_N3; Fanout = 32; COMB Node = 'SetData:inst\|count_rom\[31\]~5617'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "6.604 ns" { SDO SetData:inst|count_rom[31]~5617 } "NODE_NAME" } "" } } { "SetData.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/SetData.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.406 ns) + CELL(1.084 ns) 10.393 ns SetData:inst\|count_rom\[28\] 3 REG LC_X17_Y3_N2 5 " "Info: 3: + IC(1.406 ns) + CELL(1.084 ns) = 10.393 ns; Loc. = LC_X17_Y3_N2; Fanout = 5; REG Node = 'SetData:inst\|count_rom\[28\]'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "2.490 ns" { SetData:inst|count_rom[31]~5617 SetData:inst|count_rom[28] } "NODE_NAME" } "" } } { "SetData.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/SetData.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.773 ns 26.68 % " "Info: Total cell delay = 2.773 ns ( 26.68 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.620 ns 73.32 % " "Info: Total interconnect delay = 7.620 ns ( 73.32 % )" {  } {  } 0}  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "10.393 ns" { SDO SetData:inst|count_rom[31]~5617 SetData:inst|count_rom[28] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "10.393 ns" { SDO SDO~out0 SetData:inst|count_rom[31]~5617 SetData:inst|count_rom[28] } { 0.000ns 0.000ns 6.214ns 1.406ns } { 0.000ns 1.299ns 0.390ns 1.084ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.033 ns + " "Info: + Micro setup delay of destination is 0.033 ns" {  } { { "SetData.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/SetData.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.311 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 6.311 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns clk 1 CLK PIN_66 33 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_66; Fanout = 33; CLK Node = 'clk'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "" { clk } "NODE_NAME" } "" } } { "test.bdf" "" { Schematic "C:/Documents and Settings/mu/桌面/师兄/test/test.bdf" { { 104 -240 -72 120 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.494 ns) + CELL(0.827 ns) 2.620 ns M10MHz:inst2\|P10MHz 2 REG LC_X8_Y6_N5 158 " "Info: 2: + IC(0.494 ns) + CELL(0.827 ns) = 2.620 ns; Loc. = LC_X8_Y6_N5; Fanout = 158; REG Node = 'M10MHz:inst2\|P10MHz'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "1.321 ns" { clk M10MHz:inst2|P10MHz } "NODE_NAME" } "" } } { "M10MHz.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/M10MHz.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.062 ns) + CELL(0.629 ns) 6.311 ns SetData:inst\|count_rom\[28\] 3 REG LC_X17_Y3_N2 5 " "Info: 3: + IC(3.062 ns) + CELL(0.629 ns) = 6.311 ns; Loc. = LC_X17_Y3_N2; Fanout = 5; REG Node = 'SetData:inst\|count_rom\[28\]'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "3.691 ns" { M10MHz:inst2|P10MHz SetData:inst|count_rom[28] } "NODE_NAME" } "" } } { "SetData.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/SetData.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.755 ns 43.65 % " "Info: Total cell delay = 2.755 ns ( 43.65 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.556 ns 56.35 % " "Info: Total interconnect delay = 3.556 ns ( 56.35 % )" {  } {  } 0}  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "6.311 ns" { clk M10MHz:inst2|P10MHz SetData:inst|count_rom[28] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "6.311 ns" { clk clk~out0 M10MHz:inst2|P10MHz SetData:inst|count_rom[28] } { 0.000ns 0.000ns 0.494ns 3.062ns } { 0.000ns 1.299ns 0.827ns 0.629ns } } }  } 0}  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "10.393 ns" { SDO SetData:inst|count_rom[31]~5617 SetData:inst|count_rom[28] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "10.393 ns" { SDO SDO~out0 SetData:inst|count_rom[31]~5617 SetData:inst|count_rom[28] } { 0.000ns 0.000ns 6.214ns 1.406ns } { 0.000ns 1.299ns 0.390ns 1.084ns } } } { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "6.311 ns" { clk M10MHz:inst2|P10MHz SetData:inst|count_rom[28] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "6.311 ns" { clk clk~out0 M10MHz:inst2|P10MHz SetData:inst|count_rom[28] } { 0.000ns 0.000ns 0.494ns 3.062ns } { 0.000ns 1.299ns 0.827ns 0.629ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk SDO_out\[15\] SetData:inst\|SDO_out\[15\] 12.247 ns register " "Info: tco from clock \"clk\" to destination pin \"SDO_out\[15\]\" through register \"SetData:inst\|SDO_out\[15\]\" is 12.247 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.311 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 6.311 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns clk 1 CLK PIN_66 33 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_66; Fanout = 33; CLK Node = 'clk'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "" { clk } "NODE_NAME" } "" } } { "test.bdf" "" { Schematic "C:/Documents and Settings/mu/桌面/师兄/test/test.bdf" { { 104 -240 -72 120 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.494 ns) + CELL(0.827 ns) 2.620 ns M10MHz:inst2\|P10MHz 2 REG LC_X8_Y6_N5 158 " "Info: 2: + IC(0.494 ns) + CELL(0.827 ns) = 2.620 ns; Loc. = LC_X8_Y6_N5; Fanout = 158; REG Node = 'M10MHz:inst2\|P10MHz'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "1.321 ns" { clk M10MHz:inst2|P10MHz } "NODE_NAME" } "" } } { "M10MHz.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/M10MHz.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.062 ns) + CELL(0.629 ns) 6.311 ns SetData:inst\|SDO_out\[15\] 3 REG LC_X22_Y5_N1 1 " "Info: 3: + IC(3.062 ns) + CELL(0.629 ns) = 6.311 ns; Loc. = LC_X22_Y5_N1; Fanout = 1; REG Node = 'SetData:inst\|SDO_out\[15\]'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "3.691 ns" { M10MHz:inst2|P10MHz SetData:inst|SDO_out[15] } "NODE_NAME" } "" } } { "SetData.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/SetData.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.755 ns 43.65 % " "Info: Total cell delay = 2.755 ns ( 43.65 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.556 ns 56.35 % " "Info: Total interconnect delay = 3.556 ns ( 56.35 % )" {  } {  } 0}  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "6.311 ns" { clk M10MHz:inst2|P10MHz SetData:inst|SDO_out[15] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "6.311 ns" { clk clk~out0 M10MHz:inst2|P10MHz SetData:inst|SDO_out[15] } { 0.000ns 0.000ns 0.494ns 3.062ns } { 0.000ns 1.299ns 0.827ns 0.629ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.198 ns + " "Info: + Micro clock to output delay of source is 0.198 ns" {  } { { "SetData.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/SetData.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.738 ns + Longest register pin " "Info: + Longest register to pin delay is 5.738 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SetData:inst\|SDO_out\[15\] 1 REG LC_X22_Y5_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y5_N1; Fanout = 1; REG Node = 'SetData:inst\|SDO_out\[15\]'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "" { SetData:inst|SDO_out[15] } "NODE_NAME" } "" } } { "SetData.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/SetData.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.873 ns) + CELL(1.865 ns) 5.738 ns SDO_out\[15\] 2 PIN PIN_100 0 " "Info: 2: + IC(3.873 ns) + CELL(1.865 ns) = 5.738 ns; Loc. = PIN_100; Fanout = 0; PIN Node = 'SDO_out\[15\]'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "5.738 ns" { SetData:inst|SDO_out[15] SDO_out[15] } "NODE_NAME" } "" } } { "test.bdf" "" { Schematic "C:/Documents and Settings/mu/桌面/师兄/test/test.bdf" { { 248 816 992 264 "SDO_out\[23..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.865 ns 32.50 % " "Info: Total cell delay = 1.865 ns ( 32.50 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.873 ns 67.50 % " "Info: Total interconnect delay = 3.873 ns ( 67.50 % )" {  } {  } 0}  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "5.738 ns" { SetData:inst|SDO_out[15] SDO_out[15] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "5.738 ns" { SetData:inst|SDO_out[15] SDO_out[15] } { 0.000ns 3.873ns } { 0.000ns 1.865ns } } }  } 0}  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "6.311 ns" { clk M10MHz:inst2|P10MHz SetData:inst|SDO_out[15] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "6.311 ns" { clk clk~out0 M10MHz:inst2|P10MHz SetData:inst|SDO_out[15] } { 0.000ns 0.000ns 0.494ns 3.062ns } { 0.000ns 1.299ns 0.827ns 0.629ns } } } { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "5.738 ns" { SetData:inst|SDO_out[15] SDO_out[15] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "5.738 ns" { SetData:inst|SDO_out[15] SDO_out[15] } { 0.000ns 3.873ns } { 0.000ns 1.865ns } } }  } 0}