test.fit.qmsg

利用Verilog HDL对AD7705进行控制ADC采样

{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "9 unused 3.30 0 9 0 " "Info: Number of I/O pins in group: 9 (unused VREF, 3.30 VCCIO, 0 input, 9 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 0 14 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  14 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.30V 16 1 " "Info: I/O bank number 2 does not use VREF pins and has 3.30V VCCIO pins. 16 total pin(s) used --  1 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 3.30V 5 12 " "Info: I/O bank number 3 does not use VREF pins and has 3.30V VCCIO pins. 5 total pin(s) used --  12 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 17 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "9.148 ns register register " "Info: Estimated most critical path is register to register delay of 9.148 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SetData:inst\|count_rom\[24\] 1 REG LAB_X17_Y4 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X17_Y4; Fanout = 4; REG Node = 'SetData:inst\|count_rom\[24\]'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "" { SetData:inst|count_rom[24] } "NODE_NAME" } "" } } { "SetData.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/SetData.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.522 ns) 1.284 ns SetData:inst\|LessThan~4628 2 COMB LAB_X17_Y3 2 " "Info: 2: + IC(0.762 ns) + CELL(0.522 ns) = 1.284 ns; Loc. = LAB_X17_Y3; Fanout = 2; COMB Node = 'SetData:inst\|LessThan~4628'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "1.284 ns" { SetData:inst|count_rom[24] SetData:inst|LessThan~4628 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.729 ns) + CELL(0.522 ns) 2.535 ns SetData:inst\|LessThan~4630 3 COMB LAB_X17_Y7 6 " "Info: 3: + IC(0.729 ns) + CELL(0.522 ns) = 2.535 ns; Loc. = LAB_X17_Y7; Fanout = 6; COMB Node = 'SetData:inst\|LessThan~4630'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "1.251 ns" { SetData:inst|LessThan~4628 SetData:inst|LessThan~4630 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.066 ns) + CELL(0.522 ns) 3.123 ns SetData:inst\|CS~461 4 COMB LAB_X17_Y7 3 " "Info: 4: + IC(0.066 ns) + CELL(0.522 ns) = 3.123 ns; Loc. = LAB_X17_Y7; Fanout = 3; COMB Node = 'SetData:inst\|CS~461'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "0.588 ns" { SetData:inst|LessThan~4630 SetData:inst|CS~461 } "NODE_NAME" } "" } } { "SetData.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/SetData.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.198 ns) + CELL(0.390 ns) 3.711 ns SetData:inst\|reduce_nor~214 5 COMB LAB_X17_Y7 3 " "Info: 5: + IC(0.198 ns) + CELL(0.390 ns) = 3.711 ns; Loc. = LAB_X17_Y7; Fanout = 3; COMB Node = 'SetData:inst\|reduce_nor~214'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "0.588 ns" { SetData:inst|CS~461 SetData:inst|reduce_nor~214 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.959 ns) + CELL(0.258 ns) 4.928 ns SetData:inst\|reduce_nor~218 6 COMB LAB_X17_Y6 6 " "Info: 6: + IC(0.959 ns) + CELL(0.258 ns) = 4.928 ns; Loc. = LAB_X17_Y6; Fanout = 6; COMB Node = 'SetData:inst\|reduce_nor~218'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "1.217 ns" { SetData:inst|reduce_nor~214 SetData:inst|reduce_nor~218 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.976 ns) + CELL(0.258 ns) 6.162 ns SetData:inst\|data~589 7 COMB LAB_X18_Y8 2 " "Info: 7: + IC(0.976 ns) + CELL(0.258 ns) = 6.162 ns; Loc. = LAB_X18_Y8; Fanout = 2; COMB Node = 'SetData:inst\|data~589'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "1.234 ns" { SetData:inst|reduce_nor~218 SetData:inst|data~589 } "NODE_NAME" } "" } } { "SetData.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/SetData.vhd" 28 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.198 ns) + CELL(0.390 ns) 6.750 ns SetData:inst\|data\[31\]~591 8 COMB LAB_X18_Y8 10 " "Info: 8: + IC(0.198 ns) + CELL(0.390 ns) = 6.750 ns; Loc. = LAB_X18_Y8; Fanout = 10; COMB Node = 'SetData:inst\|data\[31\]~591'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "0.588 ns" { SetData:inst|data~589 SetData:inst|data[31]~591 } "NODE_NAME" } "" } } { "SetData.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/SetData.vhd" 28 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.066 ns) + CELL(0.522 ns) 7.338 ns SetData:inst\|count\[26\]~1046 9 COMB LAB_X18_Y8 30 " "Info: 9: + IC(0.066 ns) + CELL(0.522 ns) = 7.338 ns; Loc. = LAB_X18_Y8; Fanout = 30; COMB Node = 'SetData:inst\|count\[26\]~1046'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "0.588 ns" { SetData:inst|data[31]~591 SetData:inst|count[26]~1046 } "NODE_NAME" } "" } } { "SetData.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/SetData.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.043 ns) + CELL(0.767 ns) 9.148 ns SetData:inst\|count\[3\] 10 REG LAB_X19_Y11 8 " "Info: 10: + IC(1.043 ns) + CELL(0.767 ns) = 9.148 ns; Loc. = LAB_X19_Y11; Fanout = 8; REG Node = 'SetData:inst\|count\[3\]'" {  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "1.810 ns" { SetData:inst|count[26]~1046 SetData:inst|count[3] } "NODE_NAME" } "" } } { "SetData.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/SetData.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.151 ns 45.38 % " "Info: Total cell delay = 4.151 ns ( 45.38 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.997 ns 54.62 % " "Info: Total interconnect delay = 4.997 ns ( 54.62 % )" {  } {  } 0}  } { { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "9.148 ns" { SetData:inst|count_rom[24] SetData:inst|LessThan~4628 SetData:inst|LessThan~4630 SetData:inst|CS~461 SetData:inst|reduce_nor~214 SetData:inst|reduce_nor~218 SetData:inst|data~589 SetData:inst|data[31]~591 SetData:inst|count[26]~1046 SetData:inst|count[3] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "4 6 " "Info: Average interconnect usage is 4% of the available device resources. Peak interconnect usage is 6%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 09 16:14:31 2008 " "Info: Processing ended: Wed Apr 09 16:14:31 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0}  } {  } 0}