test.fit.qmsg

利用Verilog HDL对AD7705进行控制ADC采样

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 09 16:14:24 2008 " "Info: Processing started: Wed Apr 09 16:14:24 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off test -c test " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off test -c test" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "test EP1C3T100I7 " "Info: Selected device EP1C3T100I7 for design \"test\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C3T100C7 " "Info: Device EP1C3T100C7 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "9 30 " "Info: No exact pin location assignment(s) for 9 pins of 30 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SDO_out\[23\] " "Info: Pin SDO_out\[23\] not assigned to an exact location on the device" {  } { { "test.bdf" "" { Schematic "C:/Documents and Settings/mu/桌面/师兄/test/test.bdf" { { 248 816 992 264 "SDO_out\[23..0\]" "" } } } } { "f:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "SDO_out\[23\]" } } } } { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "" { SDO_out[23] } "NODE_NAME" } "" } } { "C:/Documents and Settings/mu/桌面/师兄/test/test.fld" "" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/test.fld" "" "" { SDO_out[23] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SDO_out\[22\] " "Info: Pin SDO_out\[22\] not assigned to an exact location on the device" {  } { { "test.bdf" "" { Schematic "C:/Documents and Settings/mu/桌面/师兄/test/test.bdf" { { 248 816 992 264 "SDO_out\[23..0\]" "" } } } } { "f:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "SDO_out\[22\]" } } } } { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "" { SDO_out[22] } "NODE_NAME" } "" } } { "C:/Documents and Settings/mu/桌面/师兄/test/test.fld" "" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/test.fld" "" "" { SDO_out[22] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SDO_out\[21\] " "Info: Pin SDO_out\[21\] not assigned to an exact location on the device" {  } { { "test.bdf" "" { Schematic "C:/Documents and Settings/mu/桌面/师兄/test/test.bdf" { { 248 816 992 264 "SDO_out\[23..0\]" "" } } } } { "f:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "SDO_out\[21\]" } } } } { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "" { SDO_out[21] } "NODE_NAME" } "" } } { "C:/Documents and Settings/mu/桌面/师兄/test/test.fld" "" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/test.fld" "" "" { SDO_out[21] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SDO_out\[20\] " "Info: Pin SDO_out\[20\] not assigned to an exact location on the device" {  } { { "test.bdf" "" { Schematic "C:/Documents and Settings/mu/桌面/师兄/test/test.bdf" { { 248 816 992 264 "SDO_out\[23..0\]" "" } } } } { "f:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "SDO_out\[20\]" } } } } { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "" { SDO_out[20] } "NODE_NAME" } "" } } { "C:/Documents and Settings/mu/桌面/师兄/test/test.fld" "" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/test.fld" "" "" { SDO_out[20] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SDO_out\[19\] " "Info: Pin SDO_out\[19\] not assigned to an exact location on the device" {  } { { "test.bdf" "" { Schematic "C:/Documents and Settings/mu/桌面/师兄/test/test.bdf" { { 248 816 992 264 "SDO_out\[23..0\]" "" } } } } { "f:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "SDO_out\[19\]" } } } } { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "" { SDO_out[19] } "NODE_NAME" } "" } } { "C:/Documents and Settings/mu/桌面/师兄/test/test.fld" "" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/test.fld" "" "" { SDO_out[19] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SDO_out\[18\] " "Info: Pin SDO_out\[18\] not assigned to an exact location on the device" {  } { { "test.bdf" "" { Schematic "C:/Documents and Settings/mu/桌面/师兄/test/test.bdf" { { 248 816 992 264 "SDO_out\[23..0\]" "" } } } } { "f:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "SDO_out\[18\]" } } } } { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "" { SDO_out[18] } "NODE_NAME" } "" } } { "C:/Documents and Settings/mu/桌面/师兄/test/test.fld" "" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/test.fld" "" "" { SDO_out[18] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SDO_out\[17\] " "Info: Pin SDO_out\[17\] not assigned to an exact location on the device" {  } { { "test.bdf" "" { Schematic "C:/Documents and Settings/mu/桌面/师兄/test/test.bdf" { { 248 816 992 264 "SDO_out\[23..0\]" "" } } } } { "f:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "SDO_out\[17\]" } } } } { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "" { SDO_out[17] } "NODE_NAME" } "" } } { "C:/Documents and Settings/mu/桌面/师兄/test/test.fld" "" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/test.fld" "" "" { SDO_out[17] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SDO_out\[16\] " "Info: Pin SDO_out\[16\] not assigned to an exact location on the device" {  } { { "test.bdf" "" { Schematic "C:/Documents and Settings/mu/桌面/师兄/test/test.bdf" { { 248 816 992 264 "SDO_out\[23..0\]" "" } } } } { "f:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "SDO_out\[16\]" } } } } { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "" { SDO_out[16] } "NODE_NAME" } "" } } { "C:/Documents and Settings/mu/桌面/师兄/test/test.fld" "" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/test.fld" "" "" { SDO_out[16] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SDO_out\[4\] " "Info: Pin SDO_out\[4\] not assigned to an exact location on the device" {  } { { "test.bdf" "" { Schematic "C:/Documents and Settings/mu/桌面/师兄/test/test.bdf" { { 248 816 992 264 "SDO_out\[23..0\]" "" } } } } { "f:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "SDO_out\[4\]" } } } } { "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/mu/桌面/师兄/test/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/mu/桌面/师兄/test/db/test.quartus_db" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/" "" "" { SDO_out[4] } "NODE_NAME" } "" } } { "C:/Documents and Settings/mu/桌面/师兄/test/test.fld" "" { Floorplan "C:/Documents and Settings/mu/桌面/师兄/test/test.fld" "" "" { SDO_out[4] } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 66 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN 66" {  } { { "test.bdf" "" { Schematic "C:/Documents and Settings/mu/桌面/师兄/test/test.bdf" { { 104 -240 -72 120 "clk" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "M10MHz:inst2\|P10MHz Global clock " "Info: Automatically promoted some destinations of signal \"M10MHz:inst2\|P10MHz\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "M10MHz:inst2\|P10MHz " "Info: Destination \"M10MHz:inst2\|P10MHz\" may be non-global or may not use global clock" {  } { { "M10MHz.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/M10MHz.vhd" 9 -1 0 } }  } 0}  } { { "M10MHz.vhd" "" { Text "C:/Documents and Settings/mu/桌面/师兄/test/M10MHz.vhd" 9 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}