test.fit.summary

利用Verilog HDL对AD7705进行控制ADC采样

Flow Status : Successful - Wed Apr 09 16:14:31 2008
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : test
Top-level Entity Name : test
Family : Cyclone
Device : EP1C3T100I7
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 462 / 2,910 ( 15 % )
Total pins : 30 / 65 ( 46 % )
Total virtual pins : 0
Total memory bits : 0 / 59,904 ( 0 % )
Total PLLs : 0 / 1 ( 0 % )