ad_control.v

来自「此程序为Verilog控制ADC的全部程序」· Verilog 代码 · 共 59 行

/*****************************
file  ad_control.v
function :  make a control bus to get value from ads807  and send it to fpga bus control with interrupt 

               *************
  clk   ------>*           *<-------ad_data  
  f_hz  ------>*           *>-------int_bus
  data  ------<*           *
               *           *
               *           *
               *************

*****************************/

module ad_control (
                   clk,          //system clock  ,classical as 48M 
                   f_hz,         //collect frequence from fpga bus control 
                   ad_data,      //data from the ads807 
                   int_bus,      //interrupt to fpga bus control 
                   data_out      //data to      fpga bus control 
                   );

input      clk;
input      [31:0]f_hz;
input      [11:0]ad_data;
output     int_bus;
reg        int_bus;
output     [11:0]data_out;
reg        [11:0]data_out;

reg        [31:0]n;              //save  n分频 
reg        [31:0]half_n ;

reg        [31:0]i;              //control words 
parameter  system_clock = 26'h2dc6c00;   //48M clock

initial
begin 
           n=26'h2dc6c00;
           i=0;
           half_n=26'h16e3600;
end 

  
always@(posedge clk) 
begin
        
        if(i<half_n)int_bus=1;
        else if(i<n)int_bus=0;
        else  i=0;
        i=i+1;
        data_out =ad_data;
        n=system_clock/f_hz;  
        half_n=n/2;
end 

  
 
endmodule