alt_u_div_2ue.tdf

此程序为Verilog控制ADC的全部程序

	prestg[1023..0]	: WIRE;
	quotient_tmp[31..0]	: WIRE;
	sel[1055..0]	: WIRE;
	selnose[1055..0]	: WIRE;
	StageIn[1055..0]	: WIRE;
	StageIn_tmp[1055..0]	: WIRE;
	StageOut[1023..0]	: WIRE;

BEGIN 
	add_sub_0.dataa[0..0] = NumeratorIn[31..31];
	add_sub_0.datab[0..0] = DenominatorIn[0..0];
	add_sub_1.dataa[] = ( StageIn[32..32], NumeratorIn[62..62]);
	add_sub_1.datab[1..0] = DenominatorIn[34..33];
	add_sub_10.dataa[] = ( StageIn[329..320], NumeratorIn[341..341]);
	add_sub_10.datab[10..0] = DenominatorIn[340..330];
	add_sub_11.dataa[] = ( StageIn[362..352], NumeratorIn[372..372]);
	add_sub_11.datab[11..0] = DenominatorIn[374..363];
	add_sub_12.dataa[] = ( StageIn[395..384], NumeratorIn[403..403]);
	add_sub_12.datab[12..0] = DenominatorIn[408..396];
	add_sub_13.dataa[] = ( StageIn[428..416], NumeratorIn[434..434]);
	add_sub_13.datab[13..0] = DenominatorIn[442..429];
	add_sub_14.dataa[] = ( StageIn[461..448], NumeratorIn[465..465]);
	add_sub_14.datab[14..0] = DenominatorIn[476..462];
	add_sub_15.dataa[] = ( StageIn[494..480], NumeratorIn[496..496]);
	add_sub_15.datab[15..0] = DenominatorIn[510..495];
	add_sub_16.dataa[] = ( StageIn[527..512], NumeratorIn[527..527]);
	add_sub_16.datab[16..0] = DenominatorIn[544..528];
	add_sub_17.dataa[] = ( StageIn[560..544], NumeratorIn[558..558]);
	add_sub_17.datab[17..0] = DenominatorIn[578..561];
	add_sub_18.dataa[] = ( StageIn[593..576], NumeratorIn[589..589]);
	add_sub_18.datab[18..0] = DenominatorIn[612..594];
	add_sub_19.dataa[] = ( StageIn[626..608], NumeratorIn[620..620]);
	add_sub_19.datab[19..0] = DenominatorIn[646..627];
	add_sub_2.dataa[] = ( StageIn[65..64], NumeratorIn[93..93]);
	add_sub_2.datab[2..0] = DenominatorIn[68..66];
	add_sub_20.dataa[] = ( StageIn[659..640], NumeratorIn[651..651]);
	add_sub_20.datab[20..0] = DenominatorIn[680..660];
	add_sub_21.dataa[] = ( StageIn[692..672], NumeratorIn[682..682]);
	add_sub_21.datab[21..0] = DenominatorIn[714..693];
	add_sub_22.dataa[] = ( StageIn[725..704], NumeratorIn[713..713]);
	add_sub_22.datab[22..0] = DenominatorIn[748..726];
	add_sub_23.dataa[] = ( StageIn[758..736], NumeratorIn[744..744]);
	add_sub_23.datab[23..0] = DenominatorIn[782..759];
	add_sub_24.dataa[] = ( StageIn[791..768], NumeratorIn[775..775]);