add_sub_3dc.tdf

此程序为Verilog控制ADC的全部程序

--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone" LPM_DIRECTION="SUB" LPM_WIDTH=1 cout dataa datab result
--VERSION_BEGIN 6.0 cbx_cycloneii 2006:02:07:15:19:20:SJ cbx_lpm_add_sub 2006:01:09:11:17:20:SJ cbx_mgl 2006:04:14:11:14:36:SJ cbx_stratix 2006:02:07:15:17:04:SJ cbx_stratixii 2006:03:03:09:35:36:SJ  VERSION_END


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--  and other software and tools, and its AMPP partner logic 
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--synthesis_resources = 
SUBDESIGN add_sub_3dc
( 
	cout	:	output;
	dataa[0..0]	:	input;
	datab[0..0]	:	input;
	result[0..0]	:	output;
) 
VARIABLE 
	carry_eqn[0..0]	: WIRE;
	cin_wire	: WIRE;
	datab_node[0..0]	: WIRE;
	sum_eqn[0..0]	: WIRE;

BEGIN 
	carry_eqn[] = ( ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & cin_wire)));
	cin_wire = B"1";
	cout = carry_eqn[0..0];
	datab_node[] = (! datab[]);
	result[] = sum_eqn[];
	sum_eqn[] = ( ((dataa[0..0] $ datab_node[0..0]) $ cin_wire));
END;
--VALID FILE