📄 block1.sim.vwf

📁 此程序为Verilog控制ADC的全部程序
💻 VWF
📖 第 1 页 / 共 3 页
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TRANSITION_LIST("f_hx[11]")
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TRANSITION_LIST("f_hx[10]")
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TRANSITION_LIST("f_hx[9]")
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TRANSITION_LIST("f_hx[8]")
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TRANSITION_LIST("f_hx[7]")
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TRANSITION_LIST("f_hx[6]")
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TRANSITION_LIST("f_hx[5]")
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TRANSITION_LIST("f_hx[4]")
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TRANSITION_LIST("f_hx[3]")
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TRANSITION_LIST("f_hx[2]")
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TRANSITION_LIST("f_hx[1]")
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TRANSITION_LIST("f_hx[0]")
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TRANSITION_LIST("int_bus")
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TRANSITION_LIST("output[11]")
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TRANSITION_LIST("output[10]")
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TRANSITION_LIST("output[9]")
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TRANSITION_LIST("output[8]")
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TRANSITION_LIST("output[7]")
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TRANSITION_LIST("output[6]")
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TRANSITION_LIST("output[4]")
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TRANSITION_LIST("output[3]")
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💿 文件大小 138 K
👤 上传用户 zwaheron
📂 所属分类 VHDL/FPGA/Verilog
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#Verilog #ADC #程序 #控制
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