up3_clock.map.rpt

用vhdl设计实现的多功能电子钟

Analysis & Synthesis report for UP3_CLOCK
Tue Jun 19 10:47:07 2001
Version 6.0 Build 178 04/27/2006 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. State Machine - |UP3_CLOCK|NEXT_STATEWEEK
  8. State Machine - |UP3_CLOCK|STATE_WEEK
  9. State Machine - |UP3_CLOCK|MODIFY_DATE_NEXT
 10. State Machine - |UP3_CLOCK|MODIFY_DATE_STATE
 11. State Machine - |UP3_CLOCK|MODIFY_NEXT
 12. State Machine - |UP3_CLOCK|MODIFY_STATE
 13. State Machine - |UP3_CLOCK|next_command
 14. State Machine - |UP3_CLOCK|state
 15. State Machine - |UP3_CLOCK|ps2:U1|c_state
 16. User-Specified and Inferred Latches
 17. General Register Statistics
 18. Inverted Register Statistics
 19. Multiplexer Restructuring Statistics (Restructuring Performed)
 20. Source assignments for Top-level Entity: |UP3_CLOCK
 21. Source assignments for ps2:U1
 22. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Jun 19 10:47:06 2001    ;
; Quartus II Version          ; 6.0 Build 178 04/27/2006 SJ Full Version ;
; Revision Name               ; UP3_CLOCK                                ;
; Top-level Entity Name       ; UP3_CLOCK                                ;
; Family                      ; Cyclone                                  ;
; Total logic elements        ; 937                                      ;
; Total pins                  ; 24                                       ;