up3_clock.map.qmsg

用vhdl设计实现的多功能电子钟

{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "CHARE\[5\] data_in VCC " "Warning: Reduced register \"CHARE\[5\]\" with stuck data_in port to stuck value VCC" {  } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "CHARF\[5\] High " "Info: Power-up level of register \"CHARF\[5\]\" is not specified -- using power-up level of High to minimize register" {  } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "CHARF\[5\] data_in VCC " "Warning: Reduced register \"CHARF\[5\]\" with stuck data_in port to stuck value VCC" {  } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "CHAR40\[5\] High " "Info: Power-up level of register \"CHAR40\[5\]\" is not specified -- using power-up level of High to minimize register" {  } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "CHAR40\[5\] data_in VCC " "Warning: Reduced register \"CHAR40\[5\]\" with stuck data_in port to stuck value VCC" {  } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "CHAR41\[5\] High " "Info: Power-up level of register \"CHAR41\[5\]\" is not specified -- using power-up level of High to minimize register" {  } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "CHAR41\[5\] data_in VCC " "Warning: Reduced register \"CHAR41\[5\]\" with stuck data_in port to stuck value VCC" {  } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "CHAR42\[5\] High " "Info: Power-up level of register \"CHAR42\[5\]\" is not specified -- using power-up level of High to minimize register" {  } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "CHAR42\[5\] data_in VCC " "Warning: Reduced register \"CHAR42\[5\]\" with stuck data_in port to stuck value VCC" {  } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "CHAR43\[5\] High " "Info: Power-up level of register \"CHAR43\[5\]\" is not specified -- using power-up level of High to minimize register" {  } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "CHAR43\[5\] data_in VCC " "Warning: Reduced register \"CHAR43\[5\]\" with stuck data_in port to stuck value VCC" {  } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now