📄 up3_clock.map.qmsg
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{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "WEEK2\[5\] data_in GND " "Warning: Reduced register \"WEEK2\[5\]\" with stuck data_in port to stuck value GND" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 1215 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "WEEK3\[7\] data_in GND " "Warning: Reduced register \"WEEK3\[7\]\" with stuck data_in port to stuck value GND" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 1215 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "WEEK3\[6\] High " "Info: Power-up level of register \"WEEK3\[6\]\" is not specified -- using power-up level of High to minimize register" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 1215 -1 0 } } } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "WEEK3\[6\] data_in VCC " "Warning: Reduced register \"WEEK3\[6\]\" with stuck data_in port to stuck value VCC" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 1215 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "WEEK3\[5\] data_in GND " "Warning: Reduced register \"WEEK3\[5\]\" with stuck data_in port to stuck value GND" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 1215 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "WEEK1\[5\] data_in GND " "Warning: Reduced register \"WEEK1\[5\]\" with stuck data_in port to stuck value GND" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 1215 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "WEEK1\[6\] High " "Info: Power-up level of register \"WEEK1\[6\]\" is not specified -- using power-up level of High to minimize register" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 1215 -1 0 } } } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "WEEK1\[6\] data_in VCC " "Warning: Reduced register \"WEEK1\[6\]\" with stuck data_in port to stuck value VCC" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 1215 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "WEEK1\[7\] data_in GND " "Warning: Reduced register \"WEEK1\[7\]\" with stuck data_in port to stuck value GND" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 1215 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "LCD_RW~reg0 data_in GND " "Warning: Reduced register \"LCD_RW~reg0\" with stuck data_in port to stuck value GND" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 31 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "WEEK2\[1\] WEEK1\[4\] " "Info: Duplicate register \"WEEK2\[1\]\" merged to single register \"WEEK1\[4\]\", power-up level changed" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 1215 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "WEEK3\[0\] WEEK1\[0\] " "Info: Duplicate register \"WEEK3\[0\]\" merged to single register \"WEEK1\[0\]\", power-up level changed" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 1215 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR4E\[7\] CHAR4E\[6\] " "Info: Duplicate register \"CHAR4E\[7\]\" merged to single register \"CHAR4E\[6\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR47\[4\] CHAR4D\[0\] " "Info: Duplicate register \"CHAR47\[4\]\" merged to single register \"CHAR4D\[0\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR2\[0\] CHAR4D\[0\] " "Info: Duplicate register \"CHAR2\[0\]\" merged to single register \"CHAR4D\[0\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR44\[0\] CHAR4D\[0\] " "Info: Duplicate register \"CHAR44\[0\]\" merged to single register \"CHAR4D\[0\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR44\[4\] CHAR4D\[0\] " "Info: Duplicate register \"CHAR44\[4\]\" merged to single register \"CHAR4D\[0\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR44\[6\] CHAR4D\[0\] " "Info: Duplicate register \"CHAR44\[6\]\" merged to single register \"CHAR4D\[0\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR44\[7\] CHAR4D\[0\] " "Info: Duplicate register \"CHAR44\[7\]\" merged to single register \"CHAR4D\[0\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR4D\[2\] CHAR4D\[0\] " "Info: Duplicate register \"CHAR4D\[2\]\" merged to single register \"CHAR4D\[0\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR47\[6\] CHAR4D\[0\] " "Info: Duplicate register \"CHAR47\[6\]\" merged to single register \"CHAR4D\[0\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR2\[2\] CHAR4D\[0\] " "Info: Duplicate register \"CHAR2\[2\]\" merged to single register \"CHAR4D\[0\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR2\[6\] CHAR4D\[0\] " "Info: Duplicate register \"CHAR2\[6\]\" merged to single register \"CHAR4D\[0\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR4D\[6\] CHAR4D\[0\] " "Info: Duplicate register \"CHAR4D\[6\]\" merged to single register \"CHAR4D\[0\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR4D\[7\] CHAR4D\[0\] " "Info: Duplicate register \"CHAR4D\[7\]\" merged to single register \"CHAR4D\[0\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR2\[4\] CHAR4D\[1\] " "Info: Duplicate register \"CHAR2\[4\]\" merged to single register \"CHAR4D\[1\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR44\[2\] CHAR4D\[1\] " "Info: Duplicate register \"CHAR44\[2\]\" merged to single register \"CHAR4D\[1\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR4D\[4\] CHAR4D\[1\] " "Info: Duplicate register \"CHAR4D\[4\]\" merged to single register \"CHAR4D\[1\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR47\[2\] CHAR4D\[1\] " "Info: Duplicate register \"CHAR47\[2\]\" merged to single register \"CHAR4D\[1\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR44\[1\] CHAR4D\[1\] " "Info: Duplicate register \"CHAR44\[1\]\" merged to single register \"CHAR4D\[1\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR44\[3\] CHAR4D\[1\] " "Info: Duplicate register \"CHAR44\[3\]\" merged to single register \"CHAR4D\[1\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR44\[5\] CHAR4D\[1\] " "Info: Duplicate register \"CHAR44\[5\]\" merged to single register \"CHAR4D\[1\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR4D\[3\] CHAR4D\[1\] " "Info: Duplicate register \"CHAR4D\[3\]\" merged to single register \"CHAR4D\[1\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR4D\[5\] CHAR4D\[1\] " "Info: Duplicate register \"CHAR4D\[5\]\" merged to single register \"CHAR4D\[1\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR4C\[7\] CHAR4C\[6\] " "Info: Duplicate register \"CHAR4C\[7\]\" merged to single register \"CHAR4C\[6\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR4B\[7\] CHAR4B\[6\] " "Info: Duplicate register \"CHAR4B\[7\]\" merged to single register \"CHAR4B\[6\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHARA\[0\] CHAR4A\[0\] " "Info: Duplicate register \"CHARA\[0\]\" merged to single register \"CHAR4A\[0\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHARA\[1\] CHAR4A\[0\] " "Info: Duplicate register \"CHARA\[1\]\" merged to single register \"CHAR4A\[0\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR4A\[1\] CHAR4A\[0\] " "Info: Duplicate register \"CHAR4A\[1\]\" merged to single register \"CHAR4A\[0\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHARA\[2\] CHAR4A\[0\] " "Info: Duplicate register \"CHARA\[2\]\" merged to single register \"CHAR4A\[0\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHARA\[3\] CHAR4A\[0\] " "Info: Duplicate register \"CHARA\[3\]\" merged to single register \"CHAR4A\[0\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR4A\[2\] CHAR4A\[0\] " "Info: Duplicate register \"CHAR4A\[2\]\" merged to single register \"CHAR4A\[0\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHARA\[4\] CHAR4A\[0\] " "Info: Duplicate register \"CHARA\[4\]\" merged to single register \"CHAR4A\[0\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR4A\[3\] CHAR4A\[0\] " "Info: Duplicate register \"CHAR4A\[3\]\" merged to single register \"CHAR4A\[0\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHARA\[6\] CHAR4A\[0\] " "Info: Duplicate register \"CHARA\[6\]\" merged to single register \"CHAR4A\[0\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHARA\[7\] CHAR4A\[0\] " "Info: Duplicate register \"CHARA\[7\]\" merged to single register \"CHAR4A\[0\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR4A\[4\] CHAR4A\[0\] " "Info: Duplicate register \"CHAR4A\[4\]\" merged to single register \"CHAR4A\[0\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR4A\[6\] CHAR4A\[0\] " "Info: Duplicate register \"CHAR4A\[6\]\" merged to single register \"CHAR4A\[0\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR4A\[7\] CHAR4A\[0\] " "Info: Duplicate register \"CHAR4A\[7\]\" merged to single register \"CHAR4A\[0\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR9\[6\] CHAR4A\[0\] " "Info: Duplicate register \"CHAR9\[6\]\" merged to single register \"CHAR4A\[0\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR9\[7\] CHAR4A\[0\] " "Info: Duplicate register \"CHAR9\[7\]\" merged to single register \"CHAR4A\[0\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR8\[0\] CHAR4A\[0\] " "Info: Duplicate register \"CHAR8\[0\]\" merged to single register \"CHAR4A\[0\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR8\[4\] CHAR4A\[0\] " "Info: Duplicate register \"CHAR8\[4\]\" merged to single register \"CHAR4A\[0\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR8\[6\] CHAR4A\[0\] " "Info: Duplicate register \"CHAR8\[6\]\" merged to single register \"CHAR4A\[0\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR8\[7\] CHAR4A\[0\] " "Info: Duplicate register \"CHAR8\[7\]\" merged to single register \"CHAR4A\[0\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR47\[7\] CHAR4A\[0\] " "Info: Duplicate register \"CHAR47\[7\]\" merged to single register \"CHAR4A\[0\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR2\[7\] CHAR4A\[0\] " "Info: Duplicate register \"CHAR2\[7\]\" merged to single register \"CHAR4A\[0\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR5\[0\] CHAR4A\[0\] " "Info: Duplicate register \"CHAR5\[0\]\" merged to single register \"CHAR4A\[0\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR5\[2\] CHAR4A\[0\] " "Info: Duplicate register \"CHAR5\[2\]\" merged to single register \"CHAR4A\[0\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR5\[6\] CHAR4A\[0\] " "Info: Duplicate register \"CHAR5\[6\]\" merged to single register \"CHAR4A\[0\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR5\[7\] CHAR4A\[0\] " "Info: Duplicate register \"CHAR5\[7\]\" merged to single register \"CHAR4A\[0\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR47\[0\] CHAR4A\[0\] " "Info: Duplicate register \"CHAR47\[0\]\" merged to single register \"CHAR4A\[0\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHARA\[5\] CHAR4A\[5\] " "Info: Duplicate register \"CHARA\[5\]\" merged to single register \"CHAR4A\[5\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR9\[4\] CHAR4A\[5\] " "Info: Duplicate register \"CHAR9\[4\]\" merged to single register \"CHAR4A\[5\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR9\[5\] CHAR4A\[5\] " "Info: Duplicate register \"CHAR9\[5\]\" merged to single register \"CHAR4A\[5\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR8\[1\] CHAR4A\[5\] " "Info: Duplicate register \"CHAR8\[1\]\" merged to single register \"CHAR4A\[5\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR8\[2\] CHAR4A\[5\] " "Info: Duplicate register \"CHAR8\[2\]\" merged to single register \"CHAR4A\[5\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR8\[3\] CHAR4A\[5\] " "Info: Duplicate register \"CHAR8\[3\]\" merged to single register \"CHAR4A\[5\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR8\[5\] CHAR4A\[5\] " "Info: Duplicate register \"CHAR8\[5\]\" merged to single register \"CHAR4A\[5\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR47\[1\] CHAR4A\[5\] " "Info: Duplicate register \"CHAR47\[1\]\" merged to single register \"CHAR4A\[5\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR47\[3\] CHAR4A\[5\] " "Info: Duplicate register \"CHAR47\[3\]\" merged to single register \"CHAR4A\[5\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR47\[5\] CHAR4A\[5\] " "Info: Duplicate register \"CHAR47\[5\]\" merged to single register \"CHAR4A\[5\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR2\[1\] CHAR4A\[5\] " "Info: Duplicate register \"CHAR2\[1\]\" merged to single register \"CHAR4A\[5\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR2\[3\] CHAR4A\[5\] " "Info: Duplicate register \"CHAR2\[3\]\" merged to single register \"CHAR4A\[5\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR2\[5\] CHAR4A\[5\] " "Info: Duplicate register \"CHAR2\[5\]\" merged to single register \"CHAR4A\[5\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR5\[1\] CHAR4A\[5\] " "Info: Duplicate register \"CHAR5\[1\]\" merged to single register \"CHAR4A\[5\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR5\[3\] CHAR4A\[5\] " "Info: Duplicate register \"CHAR5\[3\]\" merged to single register \"CHAR4A\[5\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR5\[4\] CHAR4A\[5\] " "Info: Duplicate register \"CHAR5\[4\]\" merged to single register \"CHAR4A\[5\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR5\[5\] CHAR4A\[5\] " "Info: Duplicate register \"CHAR5\[5\]\" merged to single register \"CHAR4A\[5\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR49\[7\] CHAR49\[6\] " "Info: Duplicate register \"CHAR49\[7\]\" merged to single register \"CHAR49\[6\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR48\[7\] CHAR48\[6\] " "Info: Duplicate register \"CHAR48\[7\]\" merged to single register \"CHAR48\[6\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR45\[7\] CHAR45\[6\] " "Info: Duplicate register \"CHAR45\[7\]\" merged to single register \"CHAR45\[6\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR43\[7\] CHAR43\[6\] " "Info: Duplicate register \"CHAR43\[7\]\" merged to single register \"CHAR43\[6\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR42\[7\] CHAR42\[6\] " "Info: Duplicate register \"CHAR42\[7\]\" merged to single register \"CHAR42\[6\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR41\[7\] CHAR41\[6\] " "Info: Duplicate register \"CHAR41\[7\]\" merged to single register \"CHAR41\[6\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR40\[7\] CHAR40\[6\] " "Info: Duplicate register \"CHAR40\[7\]\" merged to single register \"CHAR40\[6\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHARF\[7\] CHARF\[6\] " "Info: Duplicate register \"CHARF\[7\]\" merged to single register \"CHARF\[6\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHARE\[7\] CHARE\[6\] " "Info: Duplicate register \"CHARE\[7\]\" merged to single register \"CHARE\[6\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR7\[7\] CHAR7\[6\] " "Info: Duplicate register \"CHAR7\[7\]\" merged to single register \"CHAR7\[6\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR6\[7\] CHAR6\[6\] " "Info: Duplicate register \"CHAR6\[7\]\" merged to single register \"CHAR6\[6\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR3\[7\] CHAR3\[6\] " "Info: Duplicate register \"CHAR3\[7\]\" merged to single register \"CHAR3\[6\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR1\[7\] CHAR1\[6\] " "Info: Duplicate register \"CHAR1\[7\]\" merged to single register \"CHAR1\[6\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR0\[7\] CHAR0\[6\] " "Info: Duplicate register \"CHAR0\[7\]\" merged to single register \"CHAR0\[6\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR4F\[7\] CHAR4F\[6\] " "Info: Duplicate register \"CHAR4F\[7\]\" merged to single register \"CHAR4F\[6\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR4A\[0\] CHAR4D\[0\] " "Info: Duplicate register \"CHAR4A\[0\]\" merged to single register \"CHAR4D\[0\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR4A\[5\] CHAR4D\[1\] " "Info: Duplicate register \"CHAR4A\[5\]\" merged to single register \"CHAR4D\[1\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR46\[7\] CHAR46\[6\] " "Info: Duplicate register \"CHAR46\[7\]\" merged to single register \"CHAR46\[6\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "CHAR4\[7\] CHAR4\[6\] " "Info: Duplicate register \"CHAR4\[7\]\" merged to single register \"CHAR4\[6\]\"" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} } { } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "CHAR0\[5\] High " "Info: Power-up level of register \"CHAR0\[5\]\" is not specified -- using power-up level of High to minimize register" { } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 512 -1 0 } } } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
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