up3_clock.map.qmsg

用vhdl设计实现的多功能电子钟

{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "BCD_YEAR1 UP3_CLOCK.vhd(1075) " "Warning (10492): VHDL Process Statement warning at UP3_CLOCK.vhd(1075): signal \"BCD_YEAR1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 1075 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "BCD_YEAR0 UP3_CLOCK.vhd(1076) " "Warning (10492): VHDL Process Statement warning at UP3_CLOCK.vhd(1076): signal \"BCD_YEAR0\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 1076 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "BCD_YEAR0 UP3_CLOCK.vhd(1081) " "Warning (10492): VHDL Process Statement warning at UP3_CLOCK.vhd(1081): signal \"BCD_YEAR0\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 1081 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "reset UP3_CLOCK.vhd(1268) " "Warning (10492): VHDL Process Statement warning at UP3_CLOCK.vhd(1268): signal \"reset\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 1268 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "DAY_MODE\[0\] UP3_CLOCK.vhd(1043) " "Info (10041): Verilog HDL or VHDL info at UP3_CLOCK.vhd(1043): inferred latch for \"DAY_MODE\[0\]\"" {  } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 1043 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "DAY_MODE\[1\] UP3_CLOCK.vhd(1043) " "Info (10041): Verilog HDL or VHDL info at UP3_CLOCK.vhd(1043): inferred latch for \"DAY_MODE\[1\]\"" {  } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 1043 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "DAY_MODE\[2\] UP3_CLOCK.vhd(1043) " "Info (10041): Verilog HDL or VHDL info at UP3_CLOCK.vhd(1043): inferred latch for \"DAY_MODE\[2\]\"" {  } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 1043 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ps2 ps2:U1 " "Info: Elaborating entity \"ps2\" for hierarchy \"ps2:U1\"" {  } { { "UP3_CLOCK.vhd" "U1" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 1282 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "parbit ps2.vhd(147) " "Warning (10492): VHDL Process Statement warning at ps2.vhd(147): signal \"parbit\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "ps2.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/ps2.vhd" 147 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "WEEK2\[7\] data_in GND " "Warning: Reduced register \"WEEK2\[7\]\" with stuck data_in port to stuck value GND" {  } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 1215 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "WEEK2\[6\] High " "Info: Power-up level of register \"WEEK2\[6\]\" is not specified -- using power-up level of High to minimize register" {  } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 1215 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "WEEK2\[6\] data_in VCC " "Warning: Reduced register \"WEEK2\[6\]\" with stuck data_in port to stuck value VCC" {  } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 1215 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}