up3_clock.tan.qmsg

用vhdl设计实现的多功能电子钟

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "CLK_10HZ " "Info: Detected ripple clock \"CLK_10HZ\" as buffer" {  } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 96 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "CLK_10HZ" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "CLK_400HZ " "Info: Detected ripple clock \"CLK_400HZ\" as buffer" {  } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 96 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "CLK_400HZ" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_48Mhz register BCD_MON1\[3\] register BCD_DAY0\[1\] 69.77 MHz 14.332 ns Internal " "Info: Clock \"clk_48Mhz\" has Internal fmax of 69.77 MHz between source register \"BCD_MON1\[3\]\" and destination register \"BCD_DAY0\[1\]\" (period= 14.332 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.071 ns + Longest register register " "Info: + Longest register to register delay is 14.071 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns BCD_MON1\[3\] 1 REG LC_X20_Y7_N4 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y7_N4; Fanout = 4; REG Node = 'BCD_MON1\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { BCD_MON1[3] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.181 ns) + CELL(0.590 ns) 1.771 ns Equal18~32 2 COMB LC_X23_Y7_N8 5 " "Info: 2: + IC(1.181 ns) + CELL(0.590 ns) = 1.771 ns; Loc. = LC_X23_Y7_N8; Fanout = 5; COMB Node = 'Equal18~32'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.771 ns" { BCD_MON1[3] Equal18~32 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.773 ns) + CELL(0.292 ns) 2.836 ns Mux12~205 3 COMB LC_X24_Y7_N6 6 " "Info: 3: + IC(0.773 ns) + CELL(0.292 ns) = 2.836 ns; Loc. = LC_X24_Y7_N6; Fanout = 6; COMB Node = 'Mux12~205'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.065 ns" { Equal18~32 Mux12~205 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 1045 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.995 ns) 7.831 ns comb_8249 4 COMB LOOP LC_X24_Y4_N7 19 " "Info: 4: + IC(0.000 ns) + CELL(4.995 ns) = 7.831 ns; Loc. = LC_X24_Y4_N7; Fanout = 19; COMB LOOP Node = 'comb_8249'" { { "Info" "ITDB_PART_OF_SCC" "comb_8249 LC_X24_Y4_N7 " "Info: Loc. = LC_X24_Y4_N7; Node \"comb_8249\"" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { comb_8249 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { comb_8249 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 1043 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.995 ns" { Mux12~205 comb_8249 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 1043 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.374 ns) + CELL(0.292 ns) 9.497 ns BCD_DAY0\[1\]~6239 5 COMB LC_X23_Y5_N2 3 " "Info: 5: + IC(1.374 ns) + CELL(0.292 ns) = 9.497 ns; Loc. = LC_X23_Y5_N2; Fanout = 3; COMB Node = 'BCD_DAY0\[1\]~6239'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.666 ns" { comb_8249 BCD_DAY0[1]~6239 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.119 ns) + CELL(0.292 ns) 10.908 ns BCD_DAY0\[1\]~6230 6 COMB LC_X21_Y5_N0 1 " "Info: 6: + IC(1.119 ns) + CELL(0.292 ns) = 10.908 ns; Loc. = LC_X21_Y5_N0; Fanout = 1; COMB Node = 'BCD_DAY0\[1\]~6230'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.411 ns" { BCD_DAY0[1]~6239 BCD_DAY0[1]~6230 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.243 ns) + CELL(0.292 ns) 12.443 ns BCD_DAY0\[1\]~6235 7 COMB LC_X22_Y4_N8 1 " "Info: 7: + IC(1.243 ns) + CELL(0.292 ns) = 12.443 ns; Loc. = LC_X22_Y4_N8; Fanout = 1; COMB Node = 'BCD_DAY0\[1\]~6235'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.535 ns" { BCD_DAY0[1]~6230 BCD_DAY0[1]~6235 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 12.739 ns BCD_DAY0\[1\]~6236 8 COMB LC_X22_Y4_N9 3 " "Info: 8: + IC(0.182 ns) + CELL(0.114 ns) = 12.739 ns; Loc. = LC_X22_Y4_N9; Fanout = 3; COMB Node = 'BCD_DAY0\[1\]~6236'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.296 ns" { BCD_DAY0[1]~6235 BCD_DAY0[1]~6236 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.465 ns) + CELL(0.867 ns) 14.071 ns BCD_DAY0\[1\] 9 REG LC_X22_Y4_N4 7 " "Info: 9: + IC(0.465 ns) + CELL(0.867 ns) = 14.071 ns; Loc. = LC_X22_Y4_N4; Fanout = 7; REG Node = 'BCD_DAY0\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.332 ns" { BCD_DAY0[1]~6236 BCD_DAY0[1] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.734 ns ( 54.96 % ) " "Info: Total cell delay = 7.734 ns ( 54.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.337 ns ( 45.04 % ) " "Info: Total interconnect delay = 6.337 ns ( 45.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "14.071 ns" { BCD_MON1[3] Equal18~32 Mux12~205 comb_8249 BCD_DAY0[1]~6239 BCD_DAY0[1]~6230 BCD_DAY0[1]~6235 BCD_DAY0[1]~6236 BCD_DAY0[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "14.071 ns" { BCD_MON1[3] Equal18~32 Mux12~205 comb_8249 BCD_DAY0[1]~6239 BCD_DAY0[1]~6230 BCD_DAY0[1]~6235 BCD_DAY0[1]~6236 BCD_DAY0[1] } { 0.000ns 1.181ns 0.773ns 0.000ns 1.374ns 1.119ns 1.243ns 0.182ns 0.465ns } { 0.000ns 0.590ns 0.292ns 4.995ns 0.292ns 0.292ns 0.292ns 0.114ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_48Mhz destination 12.620 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_48Mhz\" to destination register is 12.620 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_48Mhz 1 CLK PIN_29 51 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 51; CLK Node = 'clk_48Mhz'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk_48Mhz } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.722 ns) + CELL(0.935 ns) 3.126 ns CLK_400HZ 2 REG LC_X6_Y7_N6 105 " "Info: 2: + IC(0.722 ns) + CELL(0.935 ns) = 3.126 ns; Loc. = LC_X6_Y7_N6; Fanout = 105; REG Node = 'CLK_400HZ'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.657 ns" { clk_48Mhz CLK_400HZ } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 96 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.351 ns) + CELL(0.935 ns) 8.412 ns CLK_10HZ 3 REG LC_X8_Y10_N2 287 " "Info: 3: + IC(4.351 ns) + CELL(0.935 ns) = 8.412 ns; Loc. = LC_X8_Y10_N2; Fanout = 287; REG Node = 'CLK_10HZ'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.286 ns" { CLK_400HZ CLK_10HZ } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 96 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.497 ns) + CELL(0.711 ns) 12.620 ns BCD_DAY0\[1\] 4 REG LC_X22_Y4_N4 7 " "Info: 4: + IC(3.497 ns) + CELL(0.711 ns) = 12.620 ns; Loc. = LC_X22_Y4_N4; Fanout = 7; REG Node = 'BCD_DAY0\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.208 ns" { CLK_10HZ BCD_DAY0[1] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns ( 32.09 % ) " "Info: Total cell delay = 4.050 ns ( 32.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.570 ns ( 67.91 % ) " "Info: Total interconnect delay = 8.570 ns ( 67.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.620 ns" { clk_48Mhz CLK_400HZ CLK_10HZ BCD_DAY0[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.620 ns" { clk_48Mhz clk_48Mhz~out0 CLK_400HZ CLK_10HZ BCD_DAY0[1] } { 0.000ns 0.000ns 0.722ns 4.351ns 3.497ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_48Mhz source 12.620 ns - Longest register " "Info: - Longest clock path from clock \"clk_48Mhz\" to source register is 12.620 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_48Mhz 1 CLK PIN_29 51 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 51; CLK Node = 'clk_48Mhz'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk_48Mhz } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.722 ns) + CELL(0.935 ns) 3.126 ns CLK_400HZ 2 REG LC_X6_Y7_N6 105 " "Info: 2: + IC(0.722 ns) + CELL(0.935 ns) = 3.126 ns; Loc. = LC_X6_Y7_N6; Fanout = 105; REG Node = 'CLK_400HZ'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.657 ns" { clk_48Mhz CLK_400HZ } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 96 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.351 ns) + CELL(0.935 ns) 8.412 ns CLK_10HZ 3 REG LC_X8_Y10_N2 287 " "Info: 3: + IC(4.351 ns) + CELL(0.935 ns) = 8.412 ns; Loc. = LC_X8_Y10_N2; Fanout = 287; REG Node = 'CLK_10HZ'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.286 ns" { CLK_400HZ CLK_10HZ } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 96 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.497 ns) + CELL(0.711 ns) 12.620 ns BCD_MON1\[3\] 4 REG LC_X20_Y7_N4 4 " "Info: 4: + IC(3.497 ns) + CELL(0.711 ns) = 12.620 ns; Loc. = LC_X20_Y7_N4; Fanout = 4; REG Node = 'BCD_MON1\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.208 ns" { CLK_10HZ BCD_MON1[3] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns ( 32.09 % ) " "Info: Total cell delay = 4.050 ns ( 32.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.570 ns ( 67.91 % ) " "Info: Total interconnect delay = 8.570 ns ( 67.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.620 ns" { clk_48Mhz CLK_400HZ CLK_10HZ BCD_MON1[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.620 ns" { clk_48Mhz clk_48Mhz~out0 CLK_400HZ CLK_10HZ BCD_MON1[3] } { 0.000ns 0.000ns 0.722ns 4.351ns 3.497ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.620 ns" { clk_48Mhz CLK_400HZ CLK_10HZ BCD_DAY0[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.620 ns" { clk_48Mhz clk_48Mhz~out0 CLK_400HZ CLK_10HZ BCD_DAY0[1] } { 0.000ns 0.000ns 0.722ns 4.351ns 3.497ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.620 ns" { clk_48Mhz CLK_400HZ CLK_10HZ BCD_MON1[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.620 ns" { clk_48Mhz clk_48Mhz~out0 CLK_400HZ CLK_10HZ BCD_MON1[3] } { 0.000ns 0.000ns 0.722ns 4.351ns 3.497ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 837 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 837 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "14.071 ns" { BCD_MON1[3] Equal18~32 Mux12~205 comb_8249 BCD_DAY0[1]~6239 BCD_DAY0[1]~6230 BCD_DAY0[1]~6235 BCD_DAY0[1]~6236 BCD_DAY0[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "14.071 ns" { BCD_MON1[3] Equal18~32 Mux12~205 comb_8249 BCD_DAY0[1]~6239 BCD_DAY0[1]~6230 BCD_DAY0[1]~6235 BCD_DAY0[1]~6236 BCD_DAY0[1] } { 0.000ns 1.181ns 0.773ns 0.000ns 1.374ns 1.119ns 1.243ns 0.182ns 0.465ns } { 0.000ns 0.590ns 0.292ns 4.995ns 0.292ns 0.292ns 0.292ns 0.114ns 0.867ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.620 ns" { clk_48Mhz CLK_400HZ CLK_10HZ BCD_DAY0[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.620 ns" { clk_48Mhz clk_48Mhz~out0 CLK_400HZ CLK_10HZ BCD_DAY0[1] } { 0.000ns 0.000ns 0.722ns 4.351ns 3.497ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.620 ns" { clk_48Mhz CLK_400HZ CLK_10HZ BCD_MON1[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.620 ns" { clk_48Mhz clk_48Mhz~out0 CLK_400HZ CLK_10HZ BCD_MON1[3] } { 0.000ns 0.000ns 0.722ns 4.351ns 3.497ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk_48Mhz 40 " "Warning: Circuit may not operate. Detected 40 non-operational path(s) clocked by clock \"clk_48Mhz\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "ps2:U1\|leds\[0\] KEY_BCD\[3\] clk_48Mhz 7.389 ns " "Info: Found hold time violation between source  pin or register \"ps2:U1\|leds\[0\]\" and destination pin or register \"KEY_BCD\[3\]\" for clock \"clk_48Mhz\" (Hold time is 7.389 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "9.711 ns + Largest " "Info: + Largest clock skew is 9.711 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_48Mhz destination 12.620 ns + Longest register " "Info: + Longest clock path from clock \"clk_48Mhz\" to destination register is 12.620 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_48Mhz 1 CLK PIN_29 51 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 51; CLK Node = 'clk_48Mhz'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk_48Mhz } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.722 ns) + CELL(0.935 ns) 3.126 ns CLK_400HZ 2 REG LC_X6_Y7_N6 105 " "Info: 2: + IC(0.722 ns) + CELL(0.935 ns) = 3.126 ns; Loc. = LC_X6_Y7_N6; Fanout = 105; REG Node = 'CLK_400HZ'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.657 ns" { clk_48Mhz CLK_400HZ } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 96 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.351 ns) + CELL(0.935 ns) 8.412 ns CLK_10HZ 3 REG LC_X8_Y10_N2 287 " "Info: 3: + IC(4.351 ns) + CELL(0.935 ns) = 8.412 ns; Loc. = LC_X8_Y10_N2; Fanout = 287; REG Node = 'CLK_10HZ'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.286 ns" { CLK_400HZ CLK_10HZ } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 96 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.497 ns) + CELL(0.711 ns) 12.620 ns KEY_BCD\[3\] 4 REG LC_X21_Y4_N1 22 " "Info: 4: + IC(3.497 ns) + CELL(0.711 ns) = 12.620 ns; Loc. = LC_X21_Y4_N1; Fanout = 22; REG Node = 'KEY_BCD\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.208 ns" { CLK_10HZ KEY_BCD[3] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 1271 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns ( 32.09 % ) " "Info: Total cell delay = 4.050 ns ( 32.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.570 ns ( 67.91 % ) " "Info: Total interconnect delay = 8.570 ns ( 67.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.620 ns" { clk_48Mhz CLK_400HZ CLK_10HZ KEY_BCD[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.620 ns" { clk_48Mhz clk_48Mhz~out0 CLK_400HZ CLK_10HZ KEY_BCD[3] } { 0.000ns 0.000ns 0.722ns 4.351ns 3.497ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_48Mhz source 2.909 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_48Mhz\" to source register is 2.909 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_48Mhz 1 CLK PIN_29 51 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 51; CLK Node = 'clk_48Mhz'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk_48Mhz } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.729 ns) + CELL(0.711 ns) 2.909 ns ps2:U1\|leds\[0\] 2 REG LC_X19_Y6_N3 9 " "Info: 2: + IC(0.729 ns) + CELL(0.711 ns) = 2.909 ns; Loc. = LC_X19_Y6_N3; Fanout = 9; REG Node = 'ps2:U1\|leds\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.440 ns" { clk_48Mhz ps2:U1|leds[0] } "NODE_NAME" } } { "ps2.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/ps2.vhd" 166 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.94 % ) " "Info: Total cell delay = 2.180 ns ( 74.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.729 ns ( 25.06 % ) " "Info: Total interconnect delay = 0.729 ns ( 25.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.909 ns" { clk_48Mhz ps2:U1|leds[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.909 ns" { clk_48Mhz clk_48Mhz~out0 ps2:U1|leds[0] } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.620 ns" { clk_48Mhz CLK_400HZ CLK_10HZ KEY_BCD[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.620 ns" { clk_48Mhz clk_48Mhz~out0 CLK_400HZ CLK_10HZ KEY_BCD[3] } { 0.000ns 0.000ns 0.722ns 4.351ns 3.497ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.909 ns" { clk_48Mhz ps2:U1|leds[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.909 ns" { clk_48Mhz clk_48Mhz~out0 ps2:U1|leds[0] } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "ps2.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/ps2.vhd" 166 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.113 ns - Shortest register register " "Info: - Shortest register to register delay is 2.113 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ps2:U1\|leds\[0\] 1 REG LC_X19_Y6_N3 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X19_Y6_N3; Fanout = 9; REG Node = 'ps2:U1\|leds\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ps2:U1|leds[0] } "NODE_NAME" } } { "ps2.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/ps2.vhd" 166 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.635 ns) + CELL(0.478 ns) 2.113 ns KEY_BCD\[3\] 2 REG LC_X21_Y4_N1 22 " "Info: 2: + IC(1.635 ns) + CELL(0.478 ns) = 2.113 ns; Loc. = LC_X21_Y4_N1; Fanout = 22; REG Node = 'KEY_BCD\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.113 ns" { ps2:U1|leds[0] KEY_BCD[3] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 1271 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.478 ns ( 22.62 % ) " "Info: Total cell delay = 0.478 ns ( 22.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.635 ns ( 77.38 % ) " "Info: Total interconnect delay = 1.635 ns ( 77.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.113 ns" { ps2:U1|leds[0] KEY_BCD[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.113 ns" { ps2:U1|leds[0] KEY_BCD[3] } { 0.000ns 1.635ns } { 0.000ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "UP3_CLOCK.vhd" "" { Text "E:/实验5-时钟设计now2222/实验5-时钟设计now2222/实验5-时钟设计now/实验5-时钟设计now/实验5-时钟设计1/UP3_CLOCK.vhd" 1271 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.620 ns" { clk_48Mhz CLK_400HZ CLK_10HZ KEY_BCD[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.620 ns" { clk_48Mhz clk_48Mhz~out0 CLK_400HZ CLK_10HZ KEY_BCD[3] } { 0.000ns 0.000ns 0.722ns 4.351ns 3.497ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.909 ns" { clk_48Mhz ps2:U1|leds[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.909 ns" { clk_48Mhz clk_48Mhz~out0 ps2:U1|leds[0] } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.113 ns" { ps2:U1|leds[0] KEY_BCD[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.113 ns" { ps2:U1|leds[0] KEY_BCD[3] } { 0.000ns 1.635ns } { 0.000ns 0.478ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}